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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id du1-20020a17090772c100b0084bfd56fb3bsm17667492ejc.162.2023.01.20.03.12.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 03:12:27 -0800 (PST) From: Luca Weiss Date: Fri, 20 Jan 2023 12:11:55 +0100 Subject: [PATCH 3/4] arm64: dts: qcom: sm6350: Add CCI nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221213-sm6350-cci-v1-3-e5d0c36e0c4f@fairphone.com> References: <20221213-sm6350-cci-v1-0-e5d0c36e0c4f@fairphone.com> In-Reply-To: <20221213-sm6350-cci-v1-0-e5d0c36e0c4f@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Robert Foss , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.11.2 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes for the two CCI blocks found on SM6350. The first contains two i2c busses and while the second one might also contains two busses, the downstream kernel only has one configured, and some boards use the GPIOs for the potential cci1_i2c1 one other purposes, so leave that one unconfigured. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 300ced5cda57..666c1c80e4e6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 { }; }; =20 + cci0: cci@ac4a000 { + compatible =3D "qcom,sm6350-cci", "qcom,msm8996-cci"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0 0x0ac4a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>, + <&camcc CAMCC_CCI_0_CLK_SRC>; + clock-names =3D "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + assigned-clock-rates =3D <80000000>, <37500000>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&cci0_default &cci1_default>; + pinctrl-1 =3D <&cci0_sleep &cci1_sleep>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible =3D "qcom,sm6350-cci", "qcom,msm8996-cci"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0 0x0ac4b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>, + <&camcc CAMCC_CCI_1_CLK_SRC>; + clock-names =3D "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + assigned-clock-rates =3D <80000000>, <37500000>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&cci2_default>; + pinctrl-1 =3D <&cci2_sleep>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstrea= m */ + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sm6350-camcc"; reg =3D <0 0x0ad00000 0 0x16000>; @@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; gpio-ranges =3D <&tlmm 0 0 157>; =20 + cci0_default: cci0-default-state { + pins =3D "gpio39", "gpio40"; + function =3D "cci_i2c"; + bias-pull-up; + drive-strength =3D <2>; + }; + + cci0_sleep: cci0-sleep-state { + pins =3D "gpio39", "gpio40"; + function =3D "cci_i2c"; + bias-pull-down; + drive-strength =3D <2>; + }; + + cci1_default: cci1-default-state { + pins =3D "gpio41", "gpio42"; + function =3D "cci_i2c"; + bias-pull-up; + drive-strength =3D <2>; + }; + + cci1_sleep: cci1-sleep-state { + pins =3D "gpio41", "gpio42"; + function =3D "cci_i2c"; + bias-pull-down; + drive-strength =3D <2>; + }; + + cci2_default: cci2-default-state { + pins =3D "gpio43", "gpio44"; + function =3D "cci_i2c"; + bias-pull-up; + drive-strength =3D <2>; + }; + + cci2_sleep: cci2-sleep-state { + pins =3D "gpio43", "gpio44"; + function =3D "cci_i2c"; + bias-pull-down; + drive-strength =3D <2>; + }; + sdc2_off_state: sdc2-off-state { clk-pins { pins =3D "sdc2_clk"; --=20 2.39.1