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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id 3-20020ac85643000000b003a816011d51sm1998185qtt.38.2022.12.12.10.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:23:26 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com, quic_shazhuss@quicinc.com Subject: [PATCH 4/4] arm64: dts: qcom: sc8280xp: add missing spi nodes Date: Mon, 12 Dec 2022 13:23:14 -0500 Message-Id: <20221212182314.1902632-5-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212182314.1902632-1-bmasney@redhat.com> References: <20221212182314.1902632-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the missing nodes for the spi buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 384 +++++++++++++++++++++++++ 1 file changed, 384 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 392a1509f0be..b50db09feae2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -829,6 +829,22 @@ qup2_i2c16: i2c@880000 { status =3D "disabled"; }; =20 + qup2_spi16: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00880000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup2_i2c17: i2c@884000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00884000 0 0x4000>; @@ -845,6 +861,22 @@ qup2_i2c17: i2c@884000 { status =3D "disabled"; }; =20 + qup2_spi17: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00884000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup2_uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; @@ -875,6 +907,22 @@ qup2_i2c18: i2c@888000 { status =3D "disabled"; }; =20 + qup2_spi18: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00888000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup2_i2c19: i2c@88c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0088c000 0 0x4000>; @@ -891,6 +939,22 @@ qup2_i2c19: i2c@88c000 { status =3D "disabled"; }; =20 + qup2_spi19: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0088c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup2_i2c20: i2c@890000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00890000 0 0x4000>; @@ -907,6 +971,22 @@ qup2_i2c20: i2c@890000 { status =3D "disabled"; }; =20 + qup2_spi20: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00890000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup2_i2c21: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; @@ -923,6 +1003,22 @@ qup2_i2c21: i2c@894000 { status =3D "disabled"; }; =20 + qup2_spi21: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00894000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup2_i2c22: i2c@898000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00898000 0 0x4000>; @@ -939,6 +1035,22 @@ qup2_i2c22: i2c@898000 { status =3D "disabled"; }; =20 + qup2_spi22: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00898000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup2_i2c23: i2c@89c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0089c000 0 0x4000>; @@ -954,6 +1066,22 @@ qup2_i2c23: i2c@89c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + qup2_spi23: spi@89c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0089c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; }; =20 qup0: geniqup@9c0000 { @@ -986,6 +1114,22 @@ qup0_i2c0: i2c@980000 { status =3D "disabled"; }; =20 + qup0_spi0: spi@980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00980000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup0_i2c1: i2c@984000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00984000 0 0x4000>; @@ -1002,6 +1146,22 @@ qup0_i2c1: i2c@984000 { status =3D "disabled"; }; =20 + qup0_spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00984000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup0_i2c2: i2c@988000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00988000 0 0x4000>; @@ -1018,6 +1178,22 @@ qup0_i2c2: i2c@988000 { status =3D "disabled"; }; =20 + qup0_spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00988000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup0_i2c3: i2c@98c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0098c000 0 0x4000>; @@ -1034,6 +1210,22 @@ qup0_i2c3: i2c@98c000 { status =3D "disabled"; }; =20 + qup0_spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0098c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup0_i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; @@ -1050,6 +1242,22 @@ qup0_i2c4: i2c@990000 { status =3D "disabled"; }; =20 + qup0_spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00990000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup0_i2c5: i2c@994000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00994000 0 0x4000>; @@ -1066,6 +1274,22 @@ qup0_i2c5: i2c@994000 { status =3D "disabled"; }; =20 + qup0_spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00994000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup0_i2c6: i2c@998000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00998000 0 0x4000>; @@ -1082,6 +1306,22 @@ qup0_i2c6: i2c@998000 { status =3D "disabled"; }; =20 + qup0_spi6: spi@998000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00998000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup0_i2c7: i2c@99c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0099c000 0 0x4000>; @@ -1097,6 +1337,22 @@ qup0_i2c7: i2c@99c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + qup0_spi7: spi@99c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0099c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; }; =20 qup1: geniqup@ac0000 { @@ -1129,6 +1385,22 @@ qup1_i2c8: i2c@a80000 { status =3D "disabled"; }; =20 + qup1_spi8: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a80000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup1_i2c9: i2c@a84000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a84000 0 0x4000>; @@ -1145,6 +1417,22 @@ qup1_i2c9: i2c@a84000 { status =3D "disabled"; }; =20 + qup1_spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a84000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup1_i2c10: i2c@a88000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a88000 0 0x4000>; @@ -1161,6 +1449,22 @@ qup1_i2c10: i2c@a88000 { status =3D "disabled"; }; =20 + qup1_spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a88000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup1_i2c11: i2c@a8c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a8c000 0 0x4000>; @@ -1177,6 +1481,22 @@ qup1_i2c11: i2c@a8c000 { status =3D "disabled"; }; =20 + qup1_spi11: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a8c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup1_i2c12: i2c@a90000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a90000 0 0x4000>; @@ -1193,6 +1513,22 @@ qup1_i2c12: i2c@a90000 { status =3D "disabled"; }; =20 + qup1_spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a90000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup1_i2c13: i2c@a94000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a94000 0 0x4000>; @@ -1209,6 +1545,22 @@ qup1_i2c13: i2c@a94000 { status =3D "disabled"; }; =20 + qup1_spi13: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a94000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup1_i2c14: i2c@a98000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a98000 0 0x4000>; @@ -1225,6 +1577,22 @@ qup1_i2c14: i2c@a98000 { status =3D "disabled"; }; =20 + qup1_spi14: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a98000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; + qup1_i2c15: i2c@a9c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a9c000 0 0x4000>; @@ -1240,6 +1608,22 @@ qup1_i2c15: i2c@a9c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + qup1_spi15: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a9c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + spi-max-frequency =3D <50000000>; + status =3D "disabled"; + }; }; =20 pcie4: pcie@1c00000 { --=20 2.38.1