From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9F43C4332F for ; Mon, 12 Dec 2022 12:33:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232319AbiLLMdz (ORCPT ); Mon, 12 Dec 2022 07:33:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232214AbiLLMd1 (ORCPT ); Mon, 12 Dec 2022 07:33:27 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A401637B for ; Mon, 12 Dec 2022 04:33:26 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id u5so11855849pjy.5 for ; Mon, 12 Dec 2022 04:33:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=alhK3ndi55Pn+UAZvehWSr5HT0WJYLohN8j26G14+mg=; b=qQu0KWtTsFZWdV2sgVCoDF3kIQeVcPNBTz1gprS37Trlf5kvhITuKFb77t0cE2+p0X ZrHStY317cD6gGjT64Jv9Hs+NJC1Kt8FMbQrJLmJWO+fbzjSkIXQj4xIq9171qJfb54c /bgEAeuR1jxftiiHNG961TjiKDzHELKKP9LIiGhP0K5hOgSWbjV/J84RAqRsuVahWzpD cKlgfh4+JAHYm+nmzxDZBhw1ELNJ+kyoIdFNUzbRbaAmGuuWf0w6b/1M/Fr2faKOzeJQ nIaYxdQQ9WtePfcI2YFxuOIbpk2pzKi59X4wy53mqLHUnp4cx4WVHYitfVc697GcFkYP FJCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=alhK3ndi55Pn+UAZvehWSr5HT0WJYLohN8j26G14+mg=; b=eWL92uViXEevA/DKNLRSVtlSmaoqcJrgWaqfeo6RhnHbmFrK0QdKdI+jPSCioCbS/w /qsdmxAPWSAqwItpKF/3EqI2qy3TeX9GDThpefkoFrBKuIQT2jCjj0bf1yty1R0dHSFm B41nLVRNToMgA6z2q2oz94V+v74Lq9bVPubjtaer088PxNuXUHQexGU76Allx0OjXWiD P5qAlIyjurfw3OKUKWRieHEEtUpMkYUmrfg8Kx2Ooa30uMGxzJwfrOQ3puJsIu4H038i bRady9it58Kre/E+kEkRXzliGvaeaCB/WI5dfMGPncgexj274N1JIa7o6SB6553T5+Ip HDiA== X-Gm-Message-State: ANoB5pm4C0O+pVtWmklBAch45Pn2qbIo9LoHd+w8NchAwnus3W3t5r5s /Lk2dY7leCSw1+iW/vCMA+0dwBh8CwB1s3E= X-Google-Smtp-Source: AA0mqf76W0vYctaP4uQGyTxz6lzA6fM+RGW0zYYAEweKJgILQ/VqIjWxTs1rUO32oLY1EHGDhJaxmA== X-Received: by 2002:a17:902:9b97:b0:189:9e91:762e with SMTP id y23-20020a1709029b9700b001899e91762emr15738614plp.57.1670848406037; Mon, 12 Dec 2022 04:33:26 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:25 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam Subject: [PATCH v2 01/13] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Mon, 12 Dec 2022 18:02:59 +0530 Message-Id: <20221212123311.146261-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Acked-by: Sai Prakash Ranjan Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski Reviewed-by: Andrew Halaney Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller =20 maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan =20 description: | LLCC (Last Level Cache Controller) provides last level of cache memory i= n SoC, --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C306C04FDE for ; Mon, 12 Dec 2022 12:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232265AbiLLMeJ (ORCPT ); Mon, 12 Dec 2022 07:34:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232136AbiLLMdn (ORCPT ); Mon, 12 Dec 2022 07:33:43 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF74611A34 for ; Mon, 12 Dec 2022 04:33:32 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id o1-20020a17090a678100b00219cf69e5f0so15542735pjj.2 for ; Mon, 12 Dec 2022 04:33:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oXSmdk6KZcIB/MFPzIeXJxotTRaDgWgu6sR2dSlOVP0=; b=hv669BzV1GDNlxLlrOcoVm+wZFU1E1dKb985Oy4y+3WWBByJI+PVqNf5hJY0BN4E/q 5XDqW3GoxNLDANL9Lkg/AWRhGGcDk1bRmE8HeglDBEKSMpLXNx039ApHC7e6ojmd1KhZ nP/65XIPZvSzoowT/qkd/5N3jSiueIsvUQknSWl51tUQkhEk641YuaNH9ua52p0Kj3Q0 4rpH6aJPHKdnyyIP2fY20R7F1A/PbhT6omNtN3Y9DxrPUGTmpFrEq9p1CmcXNBfgu/o8 Tvk3RDOE1/tZO4l2AouDY/HPxnAgTd3gUZ64g+wS0cFNuXJY2Ls9P6WU8Pkab/KAfjM4 ZQaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oXSmdk6KZcIB/MFPzIeXJxotTRaDgWgu6sR2dSlOVP0=; b=114JftYV3WQhS5j8Mg7NK8sU6iIKFy88Mn+823IuHTYmSpZob19fYIjNoBPUuXPVI7 OeIrjONcdr7dn2N8Il9Z/QMvdv/RFdLG0lGvFgBVpnFIj1V4Ktb0INmDJK8AUYpj8TUZ 3klg14K428LorGAdbvOLOpDNvXaeTDJ5815P78HMLu2osf2pGaPEDX2Hkuvac8hI3j1W fnaLodxtlZZJ1ONu+Oc+qqD2Jk+2yrc19dnIVeC2IYC4ziRe/c0xgLQfiIjqJgfkRQsq nkD3TsAkoSA26q9Sk9QBAcEIy7baxWXWD5vrWJC1ew5C6O00nc6nfG/NAZnUDqU+k9go cTgA== X-Gm-Message-State: ANoB5pmlFr1iro89WZSZTgojcGoi90XPLKaqXY5qdBrDH/9eMoTXzKwl 1QqbQA6Dbikt4wCXHcfeRed7 X-Google-Smtp-Source: AA0mqf5zntEOyVqCEcUq2ZkGjr9XJImnZH+hxKgv86NAMpOZsFNEIoQU+AqnBq0L2/jaq6TH8Ad3QA== X-Received: by 2002:a17:903:240c:b0:188:9806:2e2b with SMTP id e12-20020a170903240c00b0018898062e2bmr16266852plo.35.1670848412076; Mon, 12 Dec 2022 04:33:32 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:31 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 02/13] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Mon, 12 Dec 2022 18:03:00 +0530 Message-Id: <20221212123311.146261-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Register regions of the LLCC banks are located at separate addresses. Currently, the binding just lists the LLCC0 base address and specifies the size to cover all banks. This is not the correct approach since, there are holes and other registers located in between. So let's specify the base address of each LLCC bank and get rid of reg-names property as it is not needed anymore. It should be noted that the bank count differs for each SoC, so that also needs to be taken into account in the binding. Cc: # 4.19 Fixes: 7e5700ae64f6 ("dt-bindings: Documentation for qcom, llcc") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- .../bindings/arm/msm/qcom,llcc.yaml | 97 ++++++++++++++++--- 1 file changed, 83 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..260bc87629a7 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,8 @@ properties: - qcom,sm8550-llcc =20 reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region - - reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 =20 interrupts: maxItems: 1 @@ -48,7 +42,76 @@ properties: required: - compatible - reg - - reg-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region =20 additionalProperties: false =20 @@ -56,9 +119,15 @@ examples: - | #include =20 - system-cache-controller@1100000 { - compatible =3D "qcom,sdm845-llcc"; - reg =3D <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names =3D "llcc_base", "llcc_broadcast_base"; - interrupts =3D ; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + system-cache-controller@1100000 { + compatible =3D "qcom,sdm845-llcc"; + reg =3D <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + interrupts =3D ; + }; }; --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9731AC4167B for ; Mon, 12 Dec 2022 12:34:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232126AbiLLMeY (ORCPT ); Mon, 12 Dec 2022 07:34:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232174AbiLLMds (ORCPT ); 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Mon, 12 Dec 2022 04:33:37 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 03/13] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:01 +0530 Message-Id: <20221212123311.146261-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.4 Fixes: ba0411ddd133 ("arm64: dts: sdm845: Add device node for Last level ca= che controller") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 65032b94b46d..683b861e060d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,9 @@ uart15: serial@a9c000 { =20 llcc: system-cache-controller@1100000 { compatible =3D "qcom,sdm845-llcc"; - reg =3D <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CD90C4332F for ; Mon, 12 Dec 2022 12:34:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232333AbiLLMeq (ORCPT ); Mon, 12 Dec 2022 07:34:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232271AbiLLMeO (ORCPT ); Mon, 12 Dec 2022 07:34:14 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64ABA12778 for ; Mon, 12 Dec 2022 04:33:45 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id g10so11907956plo.11 for ; Mon, 12 Dec 2022 04:33:45 -0800 (PST) DKIM-Signature: v=1; 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Mon, 12 Dec 2022 04:33:44 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:43 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 04/13] arm64: dts: qcom: sc7180: Remove reg-names property from LLCC node Date: Mon, 12 Dec 2022 18:03:02 +0530 Message-Id: <20221212123311.146261-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So only change needed is to remove the reg-names property from LLCC node to conform to the binding. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.6 Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache contro= ller node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index f71cf21a8dd8..b0d524bbf051 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,6 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sc7180-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7D27C4332F for ; Mon, 12 Dec 2022 12:35:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232316AbiLLMfC (ORCPT ); Mon, 12 Dec 2022 07:35:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232307AbiLLMeZ (ORCPT ); Mon, 12 Dec 2022 07:34:25 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8287D49 for ; Mon, 12 Dec 2022 04:33:53 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id t17so11872339pjo.3 for ; Mon, 12 Dec 2022 04:33:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=26Q/WBAWFA3UhuhgRAc8FiDDi9U9JvKaLU8PlXNH5WA=; b=cmoELRfDJVkrewKkchK8Em88WWVknErid1uisKdEezigW0Dxn9Ge+SBHmjwBtQ2+E6 YxtuMsyHyxJodHk+b2wox/kY7OCLlbQ4xGpkdViVW0wO/0iKNyLEyBNvUfiDjQtR7IMk HvbBVXEETnyxk2AF22e+0l2ydtor+Lqow9QD7Kg82ZStryQDb7I94QnZBNfp0Jwu5+OO Lw+mClb/FD8uDwx+jfrK7+VrkLzIPl3WZX6DkHEld470Qh7pvK3c5cfrTyKB1XpdSYdk QrymkULlx0ur9VoOLp10l7FJ1BaTvi180PS7epFyTkIz9mmdI7C2sng3kJY/+L+or9NI Isyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=26Q/WBAWFA3UhuhgRAc8FiDDi9U9JvKaLU8PlXNH5WA=; b=kTAe7gh4iJ2/BBcQhdAdW4Nhf9agqRX3HTKgHWhq3xewRT5ojBAZGmdaAU0DKwLwMQ XrzZEIKfZvfTtE6TRKnBuIryJ24/9QJhXCor8mG/ekwRVLVO/6rIJs2MVA/5Uz7vUSAv cCd7l+FQ03v2X90F/c0/clQUhvdvH+hQ4BHv4BPd9vRNDoXOzkqPdy1TdGv7ADcThlzW KXueS9ReM+s8Ssiuy6AzWTxvLpow7z5NNAFf7kV/q9+wHlJhZPktDi25+ZZkfKG5+6c3 vnF0u//sjBjaZG8CD9R07Gk9ZANSUdVD/DclEYF2b+ILZHRL11w/OQZMkaOuIsNUChEu FW+g== X-Gm-Message-State: ANoB5pmxuW5oPXgr90W9UKwGhcwzt8M+z960kYhldjmZE0Moml4gO+qU jLJMlXftscz6GmaUnboQW9ia X-Google-Smtp-Source: AA0mqf5jgJNfNCAjLII3XBF0QHODNVOJ9pQBUhID7O5h5g2Vvqs89cTH4+jNXSevUebDUpoM1bwLGA== X-Received: by 2002:a17:902:aa91:b0:189:b8a2:27ed with SMTP id d17-20020a170902aa9100b00189b8a227edmr14858454plr.57.1670848430595; Mon, 12 Dec 2022 04:33:50 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:49 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 05/13] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:03 +0530 Message-Id: <20221212123311.146261-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.13 Fixes: 0392968dbe09 ("arm64: dts: qcom: sc7280: Add device tree node for LL= CC") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 0adf13399e64..90e11cbbaf88 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,8 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc7280-llcc"; - reg =3D <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01616C4332F for ; Mon, 12 Dec 2022 12:35:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232241AbiLLMf1 (ORCPT ); Mon, 12 Dec 2022 07:35:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232238AbiLLMe7 (ORCPT ); Mon, 12 Dec 2022 07:34:59 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9EAF12ACE for ; Mon, 12 Dec 2022 04:34:20 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id z8-20020a17090abd8800b00219ed30ce47so15542799pjr.3 for ; Mon, 12 Dec 2022 04:34:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QfIwNI7T0psn5lDqNEX4WmRlkGqyl7ZmRdxDmkjkE3o=; b=uUzlkjM9xadP/wsfePCnqjzwimre9NyLsWAauCXIMA4K2H4sdT5xEbloK1SqvMpiI1 RbnWr8fQlEusmTFxO97E6HQ1SY+VLLpx6sUhuDJqsaXMoJP0o5up0rCoTYybXD16bjSA aShFXmtsF5KPZSAIn9B2I/d31rGvMztJVH6vtfl/b++okd4nu9Kk9FPoR8TXLQATuheJ r7UTt35dMuC18r94SFLCEwbfYUALLkwJ6XlpjFzImo2IStVCik4eblWALX0L9c+bkNeQ GGFJuMsb9mYhEuTkKtqKmMrm0wzFYLXUM8ja/vhaEuUngg7DDEcLEW3cLBDuCMUUESHN k2nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QfIwNI7T0psn5lDqNEX4WmRlkGqyl7ZmRdxDmkjkE3o=; b=O4HVN9nKsBb7kYs5VR3MkexpeCbVnFEY5r7g1QZuoVpez/+bHbrn9981l7KoEW6Z0L 2FDabdggrdp30jMHjt8RL9G903PV15ceCHP+nb0NR9eY3KtTULaXaHPW3egI5vS018A6 n/cmdT4SNHBGC2eE77r2o33j4pR8RbTnkkCDC7Tx4wQ1qfTxjFKzhLb5IXBQ9J8UYHG7 9lQHKHySNnOGiWoH/ympZNh9hq1kNA5YW3J5jQTE9I6NY5xIXX3p1diGKg+KMTrQ2GdC gxdk1eJ0UYLI0uW/pU54SRMYLvzdVha1IbaKPjzYXLpHrWZ4vlBKAJBGKK/OSK80j/ow kDQw== X-Gm-Message-State: ANoB5plglkMp7A6EL+fk+7Gnv8Zer+ik0l2prIDWTfVurcc23SNLb5xl Mbyic+jhKpxBexdF+A+fB0ax X-Google-Smtp-Source: AA0mqf4rE6OP22oNrLonHgu1sGCKwOejdojpWXX0Em5PntzhDOwfs6CtZJREOlEYmIQSwLoJpiBijw== X-Received: by 2002:a17:902:6bc8:b0:188:d2b3:26c1 with SMTP id m8-20020a1709026bc800b00188d2b326c1mr15270890plt.10.1670848437579; Mon, 12 Dec 2022 04:33:57 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:56 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 06/13] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:04 +0530 Message-Id: <20221212123311.146261-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 6.0 Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 109c9d2b684d..f8731cbccce9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,11 @@ opp-6 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc8280xp-llcc"; - reg =3D <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B8DAC4167B for ; Mon, 12 Dec 2022 12:35:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232178AbiLLMfp (ORCPT ); Mon, 12 Dec 2022 07:35:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232165AbiLLMfH (ORCPT ); Mon, 12 Dec 2022 07:35:07 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A45B812630 for ; Mon, 12 Dec 2022 04:34:31 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id b13-20020a17090a5a0d00b0021906102d05so12030915pjd.5 for ; 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Mon, 12 Dec 2022 04:34:03 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:03 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 07/13] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:05 +0530 Message-Id: <20221212123311.146261-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.11 Fixes: bb1f7cf68a2d ("arm64: dts: qcom: sm8150: Add LLC support for sm8150") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index a0c57fb798d3..958655bf5b1a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,9 @@ mmss_noc: interconnect@1740000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8150-llcc"; - reg =3D <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; interrupts =3D ; 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Mon, 12 Dec 2022 04:34:10 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:09 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 08/13] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:06 +0530 Message-Id: <20221212123311.146261-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.12 Fixes: 0085a33a25cc ("arm64: dts: qcom: sm8250: Add support for LLCC block") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index dab5579946f3..439ca5f6000e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,9 @@ usb_1_dwc3: usb@a600000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8250-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; }; =20 usb_2: usb@a8f8800 { --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D806C4332F for ; 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Mon, 12 Dec 2022 04:34:16 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:15 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 09/13] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:07 +0530 Message-Id: <20221212123311.146261-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.17 Fixes: 9ac8999e8d6c ("arm64: dts: qcom: sm8350: Add LLCC node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 245dce24ec59..7f76778e1bc8 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,9 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8350-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; }; =20 usb_1: usb@a6f8800 { --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C097C4332F for ; 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Mon, 12 Dec 2022 04:34:22 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 10/13] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:08 +0530 Message-Id: <20221212123311.146261-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.18 Fixes: 1dc3e50eb680 ("arm64: dts: qcom: sm8450: Add LLCC/system-cache-contr= oller node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 570475040d95..30685857021a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,9 @@ gem_noc: interconnect@19100000 { =20 system-cache-controller@19200000 { compatible =3D "qcom,sm8450-llcc"; - reg =3D <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; interrupts =3D ; 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Mon, 12 Dec 2022 04:34:29 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:28 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 11/13] arm64: dts: qcom: sm6350: Remove reg-names property from LLCC node Date: Mon, 12 Dec 2022 18:03:09 +0530 Message-Id: <20221212123311.146261-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So only change needed is to remove the reg-names property from LLCC node to conform to the binding. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.16 Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Reviewed-by: Sai Prakash Ranjan Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 43324bf291c3..1f39627cd7c6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,6 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sm6350-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; }; =20 gem_noc: interconnect@9680000 { --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F45CC4332F for ; Mon, 12 Dec 2022 12:36:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232455AbiLLMgN (ORCPT ); Mon, 12 Dec 2022 07:36:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232355AbiLLMfY (ORCPT ); Mon, 12 Dec 2022 07:35:24 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26A9362CB for ; Mon, 12 Dec 2022 04:34:43 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id t2so8933343ply.2 for ; Mon, 12 Dec 2022 04:34:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wh6m1JcK6STNBXORkx35NkjOywagUzfiNFikKvcldrw=; b=tZ4QCiCi57c8AXrLrbQadVtl/gJetV5jfdp19zgCctxTIPtWX+IZUFLwMcQMtsf0QU yHsylcO5d6cpIAJO2tUg46uZ/SHRnlBIv9vaOSi1+V8nom1DY0+tlVE3FXvyMmtrpKPU lW7rUro7Q6LJxSMxP3XcYaCH0udFRMSMMRhHgIHQYQFU+9ILBDeSOXHtvKrmBnJjvr0r pQ95hoXf5efGxKJhnis5gINcO7es8xuDQqWTXrCZahMKCzNAS3+zBqSvb957dKlcNqNN VA57RPLouYDk1ntUhmunc9aRDxNuvNb+zL0KNqW6qaHRvKWqgTTvj99IeG1AaZcWjlRN ikRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wh6m1JcK6STNBXORkx35NkjOywagUzfiNFikKvcldrw=; b=QUlz/PGmqHxczLqpHLg8xCIj891/bR4A4CkJsAX2Bs7cf3IfMAdz6vXMjAe+bAn+7M MiWNky9C5LF6lh5uCWpZwCG0VnsxqZzjBFGvyr+0Vnoh4JSu5PwQ+0Xh9kAZqsn2Np98 DPBWt9nVVlDayrhjkyLXax6wkH7hzFGsbiCQXoGmkZjuOYRcaEHpg78FXXV/5ujWIAAT xvFHBLbDTgIjtchJ14DY+4OgizNc0BTpb7E67byz4hEnAY/oZKiLe9GaTsppBGuYz2zp YrvTt3Xl1bZQHp2GyHTgiDNHyf0k/+eHHHuMLUtbKQOfOqvp3UPaaI/M7i8KetFYHOcv rv7A== X-Gm-Message-State: ANoB5pkyZATBCtdA+ZhhUWNh0KfzZ2aK5tm+Yn4Oeqif17hjxTyTOBN+ 9199E4keXAO7heT8QmpTRFfL X-Google-Smtp-Source: AA0mqf6kBOsY3V8ewIKyXxh5nzjdVMnE2nR/Bd1+ZMaYWNa/fM4K3fxQ4LlQtilUMGM35zYuQq6lXg== X-Received: by 2002:a17:902:f2ca:b0:189:ac49:fe9d with SMTP id h10-20020a170902f2ca00b00189ac49fe9dmr15186029plc.19.1670848475217; Mon, 12 Dec 2022 04:34:35 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:34 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 12/13] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Mon, 12 Dec 2022 18:03:10 +0530 Message-Id: <20221212123311.146261-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, we no longer need to rely on reg-names property and get the base addresses using index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those needs to be defined in devicetree for index from 1..N-1. Cc: # 4.20 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..5be93577fc03 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) =20 for (i =3D 0; i < reg_data.reg_cnt; i++) { synd_reg =3D reg_data.synd_reg + (i * 4); - ret =3D regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret =3D regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, i, synd_val); } =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret =3D regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret =3D regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) =20 /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret =3D regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc =3D IRQ_HANDLED; =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret =3D regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..a29f22dad7fa 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 =20 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pde= v) return 0; } =20 -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8= index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config =3D { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platfo= rm_device *pdev, .fast_io =3D true, }; =20 - base =3D devm_platform_ioremap_resource_byname(pdev, name); + base =3D devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); =20 @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; =20 drv_data =3D devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) goto err; } =20 - drv_data->regmap =3D qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret =3D PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap =3D qcom_llcc_init_mmio(pdev, i, "llcc0_base"); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); goto err; } =20 - drv_data->bcast_regmap =3D - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg =3D of_device_get_match_data(&pdev->dev); + + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_ba= nks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + drv_data->num_banks =3D num_banks; + + drv_data->regmaps =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regm= aps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret =3D -ENOMEM; + goto err; + } + + drv_data->regmaps[0] =3D regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i =3D 1; i < num_banks; i++) { + char *base =3D kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] =3D qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret =3D PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap =3D qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_b= ase"); if (IS_ERR(drv_data->bcast_regmap)) { ret =3D PTR_ERR(drv_data->bcast_regmap); goto err; } =20 - cfg =3D of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret =3D regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_H= W_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) =20 drv_data->version =3D version; =20 - ret =3D regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0= ], - &num_banks); - if (ret) - goto err; - - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; - drv_data->num_banks =3D num_banks; - llcc_cfg =3D cfg->sct_data; sz =3D cfg->size; =20 @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices =3D llcc_cfg[i].slice_id; =20 - drv_data->offsets =3D devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret =3D -ENOMEM; - goto err; - } - - for (i =3D 0; i < num_banks; i++) - drv_data->offsets[i] =3D i * BANK_OFFSET_STRIDE; - drv_data->bitmap =3D devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { =20 /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; --=20 2.25.1 From nobody Thu Sep 18 02:58:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26C46C4332F for ; Mon, 12 Dec 2022 12:36:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232397AbiLLMgb (ORCPT ); Mon, 12 Dec 2022 07:36:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232140AbiLLMfm (ORCPT ); Mon, 12 Dec 2022 07:35:42 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE6171276A for ; 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Mon, 12 Dec 2022 04:34:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam Subject: [PATCH v2 13/13] qcom: llcc/edac: Support polling mode for ECC handling Date: Mon, 12 Dec 2022 18:03:11 +0530 Message-Id: <20221212123311.146261-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosed based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Tested-by: Andrew Halaney Tested-by: Andrew Halaney # sa8540p-ride --- drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++----------- drivers/soc/qcom/llcc-qcom.c | 13 ++++++------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 5be93577fc03..f7afb5375293 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 =20 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE =3D 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int= err_type, u32 bank) return ret; } =20 -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl =3D edev_ctl; struct llcc_drv_data *drv =3D edac_dev_ctl->pvt_info; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } =20 +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data =3D pdev->dev.platform_data; @@ -356,22 +362,31 @@ static int qcom_llcc_edac_probe(struct platform_devic= e *pdev) edev_ctl->panic_on_ue =3D LLCC_ERP_PANIC_ON_UE; edev_ctl->pvt_info =3D llcc_driv_data; =20 + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq =3D llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + edac_op_state =3D EDAC_OPSTATE_INT; + } else { + /* Fall back to polling mode otherwise */ + edac_op_state =3D EDAC_OPSTATE_POLL; + edev_ctl->poll_msec =3D ECC_POLL_MSEC; + edev_ctl->edac_check =3D llcc_ecc_check; + } + rc =3D edac_device_add_device(edev_ctl); if (rc) goto out_mem; =20 platform_set_drvdata(pdev, edev_ctl); =20 - /* Request for ecc irq */ - ecc_irq =3D llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc =3D -ENODEV; - goto out_dev; - } - rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + /* Request ECC IRQ if available */ + if (ecc_irq > 0) { + rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (rc) + goto out_dev; + } =20 return rc; =20 diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a29f22dad7fa..e044e6756415 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *= pdev) goto err; =20 drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >=3D 0) { - llcc_edac =3D platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac =3D platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); =20 return 0; err: --=20 2.25.1