From nobody Thu Sep 18 05:46:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92BE9C001B2 for ; Sun, 11 Dec 2022 05:17:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbiLKFRo (ORCPT ); Sun, 11 Dec 2022 00:17:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229947AbiLKFRk (ORCPT ); Sun, 11 Dec 2022 00:17:40 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5CD530F for ; Sat, 10 Dec 2022 21:17:37 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id d82so6408778pfd.11 for ; Sat, 10 Dec 2022 21:17:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dzRPQ9kqXAkJn4h/ETexZvCxs1EzYkBcBe3bNDa0Q6s=; b=1TlpHFmZ5yScrQS9HqCOzeW/BmzDl9WwHzR2xZ4NK1VNYGjYUciYn3N+Pwc3DHyUmS zTB9UgkxMuHtm6ZkTfb49tWZNPgOdObAtuomVuW7pZUHakq53sHCi5vPBgS2f7gpAxXd IoUA9xOKn/oe7zDcs3ULFIP7Sy1yhAtkgfWBEigw43YrnPCm3ixd9EBTQpoMcBr1c/r0 2iGFiLmbnEWzbR9n9AcCwt8EEAYGg98Xj564fmwU0kCAQ1+PWxulF3Kr5eD1a3HPVCjz aZnSDrCwNGxvAPPUBoDISqaHvn1Vj25644b88brpqHf0o3qSba0SBNBmsGU95u0SDqHW ZMKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dzRPQ9kqXAkJn4h/ETexZvCxs1EzYkBcBe3bNDa0Q6s=; b=HBNwB5E8T3cYWRlGuyocSspJAc6S9lnnq0Se8cCzyTGHIiUijsZOpqDvkVj04Jof3H Vpo44iF1EL6maajZRABsB/Fu/MEtB1Al/4RInHzmOc+zz7xXRBTpZh83mlIPPxypdK8z 9cCK2STT9uy8q1jQjsCQnvUY2oXZa9ycLIO54qWlSoOCZiLbRF1mqh563iCjTu8L3aD4 NjYhq0EsLB7m8SkqWvJQkHgnnvDkqoNMOYsLbHm1s/UvgHl+a1QbNG/hz4nzkgTb7pSu HhUs3vzlIGCov8SrW4ITxEPd7YyMtZavTqPwtKZzY9ZWVDoiv+tOsyUaHa18bYDipU7f Trfw== X-Gm-Message-State: ANoB5pl2FkU/0Q9LuWZv42Y6TC0kxleSfnA2qL9Cgzjt6c3Rw9ehCrF9 gc62XdfP7u2MrxNJvgnquOsSsg== X-Google-Smtp-Source: AA0mqf6MXrftzvR7wXCSl+TVMsCVOQGG1Q6/U95FBAZ3+fsmjg/PYOl/UE+MAyppXy0qodDWmk84IA== X-Received: by 2002:aa7:8faa:0:b0:577:adb7:20dc with SMTP id t42-20020aa78faa000000b00577adb720dcmr12530853pfs.5.1670735857093; Sat, 10 Dec 2022 21:17:37 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id f125-20020a623883000000b00575d90636dcsm3463684pfa.6.2022.12.10.21.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Dec 2022 21:17:36 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH 3/3] KVM: arm64: Normalize cache configuration Date: Sun, 11 Dec 2022 14:17:00 +0900 Message-Id: <20221211051700.275761-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221211051700.275761-1-akihiko.odaki@daynix.com> References: <20221211051700.275761-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from arm64_ftr_reg_ctrel0.sys_val, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. HCR_TID2 is now always set as it is troublesome to detect the difference of cache configurations among physical CPUs. CSSELR_EL1 is now held in the memory instead of the corresponding phyisccal register as the fabricated cache configuration may have a cache level which does not exist in the physical CPU, and setting the physical CSSELR_EL1 for the level results in an UNKNOWN behavior. CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that the VMM can restore the values saved with the old kernel. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 232 ++++++++++++--------- 6 files changed, 142 insertions(+), 106 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 8aa8492dafc0..44be46c280c1 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -81,11 +81,12 @@ * SWIO: Turn set/way invalidates into set/way clean+invalidate * PTW: Take a stage2 fault if a stage1 walk steps in device memory * TID3: Trap EL1 reads of group 3 ID registers + * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1 */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 ) + HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID2) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 9bdba47f7e14..30c4598d643b 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -88,10 +88,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) if (vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 &=3D ~HCR_RW; =20 - if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || - vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 |=3D HCR_TID2; - if (kvm_has_mte(vcpu->kvm)) vcpu->arch.hcr_el2 |=3D HCR_ATA; } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 45e2136322ba..27abf81c6910 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -178,6 +178,7 @@ struct kvm_vcpu_fault_info { enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ + CLIDR_EL1, /* Cache Level ID Register */ CSSELR_EL1, /* Cache Size Selection Register */ SCTLR_EL1, /* System Control Register */ ACTLR_EL1, /* Auxiliary Control Register */ @@ -417,6 +418,9 @@ struct kvm_vcpu_arch { u64 last_steal; gpa_t base; } steal; + + /* Per-vcpu CCSIDR override or NULL */ + u32 *ccsidr; }; =20 /* @@ -621,7 +625,6 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg= , u64 *val) return false; =20 switch (reg) { - case CSSELR_EL1: *val =3D read_sysreg_s(SYS_CSSELR_EL1); break; case SCTLR_EL1: *val =3D read_sysreg_s(SYS_SCTLR_EL12); break; case CPACR_EL1: *val =3D read_sysreg_s(SYS_CPACR_EL12); break; case TTBR0_EL1: *val =3D read_sysreg_s(SYS_TTBR0_EL12); break; @@ -666,7 +669,6 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val,= int reg) return false; =20 switch (reg) { - case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index baa5b9b3dde5..147cb4c846c6 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -39,7 +39,6 @@ static inline bool ctxt_has_mte(struct kvm_cpu_context *c= txt) =20 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { - ctxt_sys_reg(ctxt, CSSELR_EL1) =3D read_sysreg(csselr_el1); ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); ctxt_sys_reg(ctxt, CPACR_EL1) =3D read_sysreg_el1(SYS_CPACR); ctxt_sys_reg(ctxt, TTBR0_EL1) =3D read_sysreg_el1(SYS_TTBR0); @@ -95,7 +94,6 @@ static inline void __sysreg_restore_user_state(struct kvm= _cpu_context *ctxt) static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); - write_sysreg(ctxt_sys_reg(ctxt, CSSELR_EL1), csselr_el1); =20 if (has_vhe() || !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 5ae18472205a..7980983dbad7 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -157,6 +157,7 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) if (sve_state) kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); kfree(sve_state); + kfree(vcpu->arch.ccsidr); } =20 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f4a7c5abcbca..e7edd9ffadc3 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include @@ -81,25 +82,64 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val,= int reg) __vcpu_sys_reg(vcpu, reg) =3D val; } =20 -/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 = */ -static u32 cache_levels; - /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 =20 /* Which cache CCSIDR represents depends on CSSELR value. */ -static u32 get_ccsidr(u32 csselr) +static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) +{ + u64 ctr_el0; + int field; + + if (vcpu->arch.ccsidr) + return vcpu->arch.ccsidr[csselr]; + + ctr_el0 =3D arm64_ftr_reg_ctrel0.sys_val; + field =3D csselr & CSSELR_EL1_InD ? CTR_EL0_IminLine_SHIFT : CTR_EL0_Dmin= Line_SHIFT; + + /* + * Fabricate a CCSIDR value as the overriding value does not exist. + * The real CCSIDR value will not be used as it can vary by the + * physical CPU which the vcpu currently resides in. + * + * The line size is determined with arm64_ftr_reg_ctrel0.sys_val, which + * should be valid for all CPUs even if they have different cache + * configuration. + * + * The associativity bits are cleared, meaning the geometry of all data + * and unified caches (which are guaranteed to be PIPT and thus + * non-aliasing) are 1 set and 1 way. + * Guests should not be doing cache operations by set/way at all, and + * for this reason, we trap them and attempt to infer the intent, so + * that we can flush the entire guest's address space at the appropriate + * time. The exposed geometry minimizes the number of the traps. + * [If guests should attempt to infer aliasing properties from the + * geometry (which is not permitted by the architecture), they would + * only do so for virtually indexed caches.] + */ + return cpuid_feature_extract_unsigned_field(ctr_el0, field) - 2; +} + +static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) { - u32 ccsidr; + u32 i; + + if (!vcpu->arch.ccsidr) { + if (val =3D=3D get_ccsidr(vcpu, csselr)) + return 0; + + vcpu->arch.ccsidr =3D + kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL); + if (!vcpu->arch.ccsidr) + return -ENOMEM; + + for (i =3D 0; i < CSSELR_MAX; i++) + vcpu->arch.ccsidr[i] =3D get_ccsidr(vcpu, i); + } =20 - /* Make sure noone else changes CSSELR during this! */ - local_irq_disable(); - write_sysreg(csselr, csselr_el1); - isb(); - ccsidr =3D read_sysreg(ccsidr_el1); - local_irq_enable(); + vcpu->arch.ccsidr[csselr] =3D val; =20 - return ccsidr; + return 0; } =20 /* @@ -1124,6 +1164,12 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, = struct sys_reg_desc const *r ID_DFR0_PERFMON_SHIFT, kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); break; + case SYS_ID_AA64MMFR2_EL1: + val &=3D ~ID_AA64MMFR2_EL1_CCIDX_MASK; + break; + case SYS_ID_MMFR4_EL1: + val &=3D ~ARM64_FEATURE_MASK(ID_MMFR4_CCIDX); + break; } =20 return val; @@ -1275,10 +1321,64 @@ static bool access_clidr(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, if (p->is_write) return write_to_read_only(vcpu, p, r); =20 - p->regval =3D read_sysreg(clidr_el1); + p->regval =3D __vcpu_sys_reg(vcpu, r->reg); return true; } =20 +/* + * Fabricate a CLIDR_EL1 value instead of using the real value, which can = vary + * by the physical CPU which the vcpu currently resides in. + */ +static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *= r) +{ + u64 dic =3D arm64_ftr_reg_ctrel0.sys_val & CTR_EL0_DIC; + u64 idc =3D arm64_ftr_reg_ctrel0.sys_val & CTR_EL0_IDC; + u64 clidr; + + if (dic && idc) { + /* + * No cache maintenance required to ensure the PoU so have only + * one unified cache level for LoC. + */ + clidr =3D 1 << CLIDR_LOC_SHIFT; + clidr |=3D CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(1); + } else { + /* + * Cache maintenance required to ensure the PoU. Let L1 be a + * separate cache to be invalidated or cleaned when ensuring + * the PoU. + */ + clidr =3D (1 << CLIDR_LOUU_SHIFT) | (1 << CLIDR_LOUIS_SHIFT); + + /* + * Instruction cache invalidation to the PoU is required so + * let L1 have an instruction cache. + */ + if (!dic) + clidr |=3D CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); + + if (idc) { + /* + * Data cache clean to the PoU is not required so + * L1 will not have data cache. Let L2 be a unified + * cache for LoC. + */ + clidr |=3D 2 << CLIDR_LOC_SHIFT; + clidr |=3D CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(2); + } else { + /* + * Data cache clean to the PoU is required so let L1 + * have a data cache. As L1 has a data cache, it can + * be marked as LoC too. + */ + clidr |=3D 1 << CLIDR_LOC_SHIFT; + clidr |=3D CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); + } + } + + __vcpu_sys_reg(vcpu, r->reg) =3D clidr; +} + static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1300,25 +1400,19 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, st= ruct sys_reg_params *p, return write_to_read_only(vcpu, p, r); =20 csselr =3D vcpu_read_sys_reg(vcpu, CSSELR_EL1); - p->regval =3D get_ccsidr(csselr); + if (csselr >=3D CSSELR_MAX) + return undef_access(vcpu, p, r); =20 - /* - * Guests should not be doing cache operations by set/way at all, and - * for this reason, we trap them and attempt to infer the intent, so - * that we can flush the entire guest's address space at the appropriate - * time. - * To prevent this trapping from causing performance problems, let's - * expose the geometry of all data and unified caches (which are - * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. - * [If guests should attempt to infer aliasing properties from the - * geometry (which is not permitted by the architecture), they would - * only do so for virtually indexed caches.] - */ - if (!(csselr & 1)) // data or unified cache - p->regval &=3D ~GENMASK(27, 3); + p->regval =3D get_ccsidr(vcpu, csselr); return true; } =20 +static void reset_ccsidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc = *r) +{ + kfree(vcpu->arch.ccsidr); + vcpu->arch.ccsidr =3D NULL; +} + static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -1603,8 +1697,9 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, =20 - { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, - { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr, reset_ccsidr }, + { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1 }, + { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, @@ -2106,6 +2201,7 @@ static const struct sys_reg_desc cp15_regs[] =3D { =20 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, + { Op1(1), CRn(0), CRm(0), Op2(2), undef_access }, { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, }; =20 @@ -2611,7 +2707,6 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, =20 FUNCTION_INVARIANT(midr_el1) FUNCTION_INVARIANT(revidr_el1) -FUNCTION_INVARIANT(clidr_el1) FUNCTION_INVARIANT(aidr_el1) =20 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) @@ -2623,7 +2718,6 @@ static void get_ctr_el0(struct kvm_vcpu *v, const str= uct sys_reg_desc *r) static struct sys_reg_desc invariant_sys_regs[] =3D { { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, - { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, }; @@ -2660,33 +2754,7 @@ static int set_invariant_sys_reg(u64 id, u64 __user = *uaddr) return 0; } =20 -static bool is_valid_cache(u32 val) -{ - u32 level, ctype; - - if (val >=3D CSSELR_MAX) - return false; - - /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ - level =3D (val >> 1); - ctype =3D (cache_levels >> (level * 3)) & 7; - - switch (ctype) { - case 0: /* No cache */ - return false; - case 1: /* Instruction cache only */ - return (val & 1); - case 2: /* Data cache only */ - case 4: /* Unified cache */ - return !(val & 1); - case 3: /* Separate instruction and data caches */ - return true; - default: /* Reserved: we can't know instruction or data. */ - return false; - } -} - -static int demux_c15_get(u64 id, void __user *uaddr) +static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val; u32 __user *uval =3D uaddr; @@ -2702,16 +2770,16 @@ static int demux_c15_get(u64 id, void __user *uaddr) return -ENOENT; val =3D (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >=3D CSSELR_MAX) return -ENOENT; =20 - return put_user(get_ccsidr(val), uval); + return put_user(get_ccsidr(vcpu, val), uval); default: return -ENOENT; } } =20 -static int demux_c15_set(u64 id, void __user *uaddr) +static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val, newval; u32 __user *uval =3D uaddr; @@ -2727,16 +2795,13 @@ static int demux_c15_set(u64 id, void __user *uaddr) return -ENOENT; val =3D (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >=3D CSSELR_MAX) return -ENOENT; =20 if (get_user(newval, uval)) return -EFAULT; =20 - /* This is also invariant: you can't change it. */ - if (newval !=3D get_ccsidr(val)) - return -EINVAL; - return 0; + return set_ccsidr(vcpu, val, newval); default: return -ENOENT; } @@ -2773,7 +2838,7 @@ int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg int err; =20 if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) - return demux_c15_get(reg->id, uaddr); + return demux_c15_get(vcpu, reg->id, uaddr); =20 err =3D get_invariant_sys_reg(reg->id, uaddr); if (err !=3D -ENOENT) @@ -2817,7 +2882,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg int err; =20 if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) - return demux_c15_set(reg->id, uaddr); + return demux_c15_set(vcpu, reg->id, uaddr); =20 err =3D set_invariant_sys_reg(reg->id, uaddr); if (err !=3D -ENOENT) @@ -2829,13 +2894,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, c= onst struct kvm_one_reg *reg =20 static unsigned int num_demux_regs(void) { - unsigned int i, count =3D 0; - - for (i =3D 0; i < CSSELR_MAX; i++) - if (is_valid_cache(i)) - count++; - - return count; + return CSSELR_MAX; } =20 static int write_demux_regids(u64 __user *uindices) @@ -2845,8 +2904,6 @@ static int write_demux_regids(u64 __user *uindices) =20 val |=3D KVM_REG_ARM_DEMUX_ID_CCSIDR; for (i =3D 0; i < CSSELR_MAX; i++) { - if (!is_valid_cache(i)) - continue; if (put_user(val | i, uindices)) return -EFAULT; uindices++; @@ -2948,7 +3005,6 @@ int kvm_sys_reg_table_init(void) { bool valid =3D true; unsigned int i; - struct sys_reg_desc clidr; =20 /* Make sure tables are unique and in order. */ valid &=3D check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), f= alse); @@ -2965,23 +3021,5 @@ int kvm_sys_reg_table_init(void) for (i =3D 0; i < ARRAY_SIZE(invariant_sys_regs); i++) invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); =20 - /* - * CLIDR format is awkward, so clean it up. See ARM B4.1.20: - * - * If software reads the Cache Type fields from Ctype1 - * upwards, once it has seen a value of 0b000, no caches - * exist at further-out levels of the hierarchy. So, for - * example, if Ctype3 is the first Cache Type field with a - * value of 0b000, the values of Ctype4 to Ctype7 must be - * ignored. - */ - get_clidr_el1(NULL, &clidr); /* Ugly... */ - cache_levels =3D clidr.val; - for (i =3D 0; i < 7; i++) - if (((cache_levels >> (i*3)) & 7) =3D=3D 0) - break; - /* Clear all higher bits. */ - cache_levels &=3D (1 << (i*3))-1; - return 0; } --=20 2.38.1