From nobody Thu Sep 18 05:46:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 719AFC4332F for ; Sun, 11 Dec 2022 05:17:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229961AbiLKFRl (ORCPT ); Sun, 11 Dec 2022 00:17:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229918AbiLKFRe (ORCPT ); Sun, 11 Dec 2022 00:17:34 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A35D113E3F for ; Sat, 10 Dec 2022 21:17:33 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id f3so6147543pgc.2 for ; Sat, 10 Dec 2022 21:17:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=GBN+ZALj8zfq0AkLO/TC4sIe3TmnWeKtF4IkOeoc8WMusywr6GhDL0Lp0DtV/b9H80 r2RSn84wFOfLraJwQzSw8Ol3XvzwwKaR78jP0W3F7pKI8ztIpMjiwY7oJlP7/fqHM3kv v/E4bchTLczJlx5W3+0bm+/4cqkf/4QcHn7pwjuA19ONjM6eRa66N9fiVQsGGUAP00z2 sx8n06LW1N+PMYFnNzR5ifRwPduryrrgDjPY0a52UjtVUFRTUVY6JNCKNyX80N7UWcZo vL8Q7NaX98ODr5ajcnt5fzUtH/F7U+JVwwZREEy10T39mJ9KC2+mK5uzHk+866J9nufQ CJhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=4vTCL7/gb0yxNm2PFZDZsPyTpVOBliIfc6ITlNOWsiQzgdC4LGRU2HRNFlCGnp4+Q9 DLinHmzgajvueA/+oqxDtOf9dspXijbM49S+UntDdE0lt6DMvrkH0yvYy51V3yKvOP59 bP1TO8SSA+sN1gYPksAcRxLv0GZTQ3HaYllWrcbGwF37LuidPWFplHvRgW2OQ+5fbiQT G5YEq/apYgeBPasOFjensLS5pd6koLQrwOCN+YR5zvYGd0nami0xBs6nImUeaICY1Lyh czkxt6Dve5NnKeVmAnxRQswxCWtvrWb2lcvBXMa5XxFYEgrzVYjDcv9AgNtxsQ/WlQKC z3Gw== X-Gm-Message-State: ANoB5pnLKaDUgJDqesnD3MjL3Uzpeq1Sa5GMmDV8kf1O0KpHiWiNDicw s5d1rCGUwcotntxXs0QX1ClPOQ== X-Google-Smtp-Source: AA0mqf5Pn3/DOoheq6ZMKTkI4FtFVRm6/0Dm0xremwLepva6byCl9K1Nn5R1XWtPEvLo7An3LPgi3Q== X-Received: by 2002:aa7:90c5:0:b0:572:6e9b:9f9e with SMTP id k5-20020aa790c5000000b005726e9b9f9emr9967229pfk.19.1670735853171; Sat, 10 Dec 2022 21:17:33 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id f125-20020a623883000000b00575d90636dcsm3463684pfa.6.2022.12.10.21.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Dec 2022 21:17:32 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH 2/3] arm64/cache: Move CLIDR macro definitions Date: Sun, 11 Dec 2022 14:16:59 +0900 Message-Id: <20221211051700.275761-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221211051700.275761-1-akihiko.odaki@daynix.com> References: <20221211051700.275761-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The macros are useful for KVM which needs to manage how CLIDR is exposed to vcpu so move them to include/asm/cache.h, which KVM can refer to. Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/cache.h | 6 ++++++ arch/arm64/kernel/cacheinfo.c | 5 ----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index c0b178d1bb4f..ab7133654a72 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -16,6 +16,12 @@ #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) =20 +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n =3D 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 97c42be71338..daa7b3f55997 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -11,11 +11,6 @@ #include =20 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ -/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n =3D 1 to 7 */ -#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) -#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) -#define CLIDR_CTYPE(clidr, level) \ - (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) =20 int cache_line_size(void) { --=20 2.38.1