From nobody Thu Sep 18 05:26:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38342C4332F for ; Sat, 10 Dec 2022 16:20:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230042AbiLJQUH (ORCPT ); Sat, 10 Dec 2022 11:20:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230037AbiLJQTb (ORCPT ); Sat, 10 Dec 2022 11:19:31 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24F6C1AA06; Sat, 10 Dec 2022 08:19:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670689154; x=1702225154; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OX7uFn6N9uY8SXcXm88RgI0VqH58t7OqQqhqDApVw/w=; b=mAsC1GMmfJSP7Reqs0bkUS83fbDDPpHcCcxGNVxbAjsWYlq7UlBV70Qk fZP9RLsFGSZfXDuwYuhB3AIlp1USc17Q8jIHMxyhaT0yGO14U91ZOP/G+ NPPSgJP3G31GuhPCiQ8+dNI3ShzjmdD9zAHpmls1EsfeRHtNqfgIcV6P3 Jq+IEzBFp+BHuigIH2+XzwuGddMnHEE1Zgn/ONPMcldFBRl9hu/fjX6LT kPTOOwHO7rHSNG/NEzveae9Rqt2TzfJkU9e1pPmiM9+OQkoqHaRDKstCI wkoguwTWytSs6+oGq+9mSRrxSZ6/Vj1OTaPxrw4cDB2AjS+ZJG2e7idfL w==; X-IronPort-AV: E=McAfee;i="6500,9779,10557"; a="318780507" X-IronPort-AV: E=Sophos;i="5.96,234,1665471600"; d="scan'208";a="318780507" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2022 08:19:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10557"; a="711208706" X-IronPort-AV: E=Sophos;i="5.96,234,1665471600"; d="scan'208";a="711208706" Received: from unknown (HELO localhost.localdomain) ([10.239.161.133]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2022 08:19:10 -0800 From: Zhang Chen To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Zhang Chen , Chao Gao , Pawan Gupta , Paolo Bonzini , Sean Christopherson , "H. Peter Anvin" , Dave Hansen , Borislav Petkov , Ingo Molnar , Thomas Gleixner Subject: [RFC PATCH 8/9] x86/kvm/vmx: Initialize SPEC_CTRL MASK for RRSBA Date: Sun, 11 Dec 2022 00:00:45 +0800 Message-Id: <20221210160046.2608762-9-chen.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221210160046.2608762-1-chen.zhang@intel.com> References: <20221210160046.2608762-1-chen.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" VMMs can address mitigations issues in migration pool by applying the needed controls whenever the guest is operating on a newer processor. If a guest is using retpoline to mitigate intra-mode BTI in CPL0, the VMM can set RRSBA_DIS_S when the guest runs on hardware which enumerates RRSBA. Signed-off-by: Zhang Chen --- arch/x86/kvm/vmx/vmx.c | 57 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 6ed6b743be0e..fb0f3b1639b9 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2007,6 +2007,20 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct= msr_data *msr_info) return 1; msr_info->data =3D vmx->msr_virtual_enumeration; break; + case MSR_VIRTUAL_MITIGATION_ENUM: + if (!msr_info->host_initiated && + !(vmx->msr_virtual_enumeration & + VIRT_ENUM_MITIGATION_CTRL_SUPPORT)) + return 1; + msr_info->data =3D vmx->msr_virtual_mitigation_enum; + break; + case MSR_VIRTUAL_MITIGATION_CTRL: + if (!msr_info->host_initiated && + !(vmx->msr_virtual_enumeration & + VIRT_ENUM_MITIGATION_CTRL_SUPPORT)) + return 1; + msr_info->data =3D vmx->msr_virtual_mitigation_ctrl; + break; default: find_uret_msr: msr =3D vmx_find_uret_msr(vmx, msr_info->index); @@ -2056,7 +2070,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) struct vmx_uret_msr *msr; int ret =3D 0; u32 msr_index =3D msr_info->index; - u64 data =3D msr_info->data; + u64 data =3D msr_info->data, arch_msr; u32 index; =20 switch (msr_index) { @@ -2390,6 +2404,46 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct= msr_data *msr_info) vmx->msr_virtual_enumeration =3D data & VIRT_ENUM_MITIGATION_CTRL_SUPPORT; break; + case MSR_VIRTUAL_MITIGATION_ENUM: + if (msr_info->host_initiated && + !(vmx->msr_virtual_enumeration & + VIRT_ENUM_MITIGATION_CTRL_SUPPORT)) + return 1; + if (data & ~MITI_ENUM_SUPPORTED) + return 1; + vmx->msr_virtual_mitigation_enum =3D data; + break; + case MSR_VIRTUAL_MITIGATION_CTRL: + if (!msr_info->host_initiated && + !(vmx->msr_virtual_enumeration & + VIRT_ENUM_MITIGATION_CTRL_SUPPORT)) + return 1; + if (data & ~MITI_CTRL_USED) + return 1; + + if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, arch_msr); + + if (data & MITI_CTRL_RETPOLINE_S_USED && + boot_cpu_has(X86_FEATURE_RRSBA_CTRL) && + arch_msr & ARCH_CAP_RRSBA) + vmx->spec_ctrl_mask |=3D SPEC_CTRL_RRSBA_DIS_S; + else + vmx->spec_ctrl_mask &=3D ~SPEC_CTRL_RRSBA_DIS_S; + + if (cpu_has_virt_spec_ctrl()) { + vmcs_write64(IA32_SPEC_CTRL_MASK, vmx->spec_ctrl_mask); + } else if (vmx->spec_ctrl_mask) { + pr_err_once("Virtual spec ctrl is missing. Cannot keep " + "bits in %llx always set\n", + vmx->spec_ctrl_mask); + vmx->spec_ctrl_mask =3D 0; + } + + vmx->spec_ctrl =3D vmx->spec_ctrl | vmx->spec_ctrl_mask; + + vmx->msr_virtual_mitigation_ctrl =3D data; + break; =20 default: find_uret_msr: @@ -4774,6 +4828,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, boo= l init_event) =20 vmx->rmode.vm86_active =3D 0; =20 + vmx->msr_virtual_mitigation_ctrl =3D 0; if (cpu_has_virt_spec_ctrl()) { vmx->spec_ctrl_mask =3D 0; vmcs_write64(IA32_SPEC_CTRL_MASK, vmx->spec_ctrl_mask); --=20 2.25.1