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([2601:18c:8380:74b0:e8e5:f40c:d741:8f07]) by smtp.gmail.com with ESMTPSA id p16-20020a05620a057000b006fee9a70343sm712718qkp.14.2022.12.09.13.54.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 13:54:06 -0800 (PST) From: Ben Wolsieffer To: linux-stm32@st-md-mailman.stormreply.com Cc: Linus Walleij , Ben Wolsieffer , Russell King , Ard Biesheuvel , "Russell King (Oracle)" , Catalin Marinas , "Steven Rostedt (Google)" , Arnd Bergmann , Masahiro Yamada , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 1/2] ARM: v7m: handle faults Date: Fri, 9 Dec 2022 16:48:12 -0500 Message-Id: <20221209214824.3444954-2-benwolsieffer@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209214824.3444954-1-benwolsieffer@gmail.com> References: <20221209214824.3444954-1-benwolsieffer@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, any fault on an ARMv7M system will trigger the invalid entry exception handler, bringing down the entire system. This patch installs real handlers for the hard fault, memmanage, bus fault and usage fault exceptions. For kernel space faults, an oops is triggered, while user space faults kill the offending process with an appropriate signal. The fault status registers are parsed to construct an appropriate message and signal. This is based on a patch from Emcraft Systems' kernel tree [1], but I have significantly reworked it. [1] https://github.com/EmcraftSystems/linux-upstream/commit/2882de1d86bd536= c855feee582d44722434c2ac9 Signed-off-by: Ben Wolsieffer --- arch/arm/include/asm/v7m.h | 29 +++++++ arch/arm/kernel/Makefile | 2 +- arch/arm/kernel/entry-v7m.S | 68 +++++++++++++++- arch/arm/kernel/traps-v7m.c | 156 ++++++++++++++++++++++++++++++++++++ 4 files changed, 250 insertions(+), 5 deletions(-) create mode 100644 arch/arm/kernel/traps-v7m.c diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h index 4512f7e1918f..b8c636a0578d 100644 --- a/arch/arm/include/asm/v7m.h +++ b/arch/arm/include/asm/v7m.h @@ -38,6 +38,35 @@ #define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17) #define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) =20 +#define V7M_SCB_CFSR 0x28 + +#define V7M_SCB_CFSR_DIVBYZERO (1 << 25) +#define V7M_SCB_CFSR_UNALIGNED (1 << 24) +#define V7M_SCB_CFSR_NOCP (1 << 19) +#define V7M_SCB_CFSR_INVPC (1 << 18) +#define V7M_SCB_CFSR_INVSTATE (1 << 17) +#define V7M_SCB_CFSR_UNDEFINSTR (1 << 16) +#define V7M_SCB_CFSR_BFARVALID (1 << 15) +#define V7M_SCB_CFSR_LSPERR (1 << 13) +#define V7M_SCB_CFSR_STKERR (1 << 12) +#define V7M_SCB_CFSR_UNSTKERR (1 << 11) +#define V7M_SCB_CFSR_IMPRECISERR (1 << 10) +#define V7M_SCB_CFSR_PRECISERR (1 << 9) +#define V7M_SCB_CFSR_IBUSERR (1 << 8) +#define V7M_SCB_CFSR_MMARVALID (1 << 7) +#define V7M_SCB_CFSR_MLSPERR (1 << 5) +#define V7M_SCB_CFSR_MSTKERR (1 << 4) +#define V7M_SCB_CFSR_MUNSTKERR (1 << 3) +#define V7M_SCB_CFSR_DACCVIOL (1 << 1) +#define V7M_SCB_CFSR_IACCVIOL (1 << 0) + +#define V7M_SCB_HFSR 0x2c +#define V7M_SCB_HFSR_FORCED (1 << 30) +#define V7M_SCB_HFSR_VECTTBL (1 << 1) + +#define V7M_SCB_MMAR 0x34 +#define V7M_SCB_BFAR 0x38 + #define V7M_xPSR_FRAMEPTRALIGN 0x00000200 #define V7M_xPSR_EXCEPTIONNO V7M_SCB_ICSR_VECTACTIVE =20 diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 48737ec800eb..6d7b06b28113 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_ATAGS_PROC) +=3D atags_proc.o obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) +=3D atags_compat.o =20 ifeq ($(CONFIG_CPU_V7M),y) -obj-y +=3D entry-v7m.o v7m.o +obj-y +=3D entry-v7m.o v7m.o traps-v7m.o else obj-y +=3D entry-armv.o endif diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index de8a60363c85..62909731cd1f 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -84,6 +84,66 @@ __irq_entry: bx lr ENDPROC(__irq_entry) =20 +__hardfault_entry: + v7m_exception_entry + + @ + @ Invoke the Hard Fault handler + @ routine called with r0 =3D struct pt_regs * + mov r0, sp + bl do_hardfault + + @ execute the pending work, including reschedule + get_thread_info tsk + mov why, #0 + b ret_to_user_from_irq +ENDPROC(__hardfault_entry) + +__memmanage_entry: + v7m_exception_entry + + @ + @ Invoke the Mem Manage handler + @ routine called with r0 =3D struct pt_regs * + mov r0, sp + bl do_memmanage + + @ execute the pending work, including reschedule + get_thread_info tsk + mov why, #0 + b ret_to_user_from_irq +ENDPROC(__memmanage_entry) + +__busfault_entry: + v7m_exception_entry + + @ + @ Invoke the Bus Fault handler + @ routine called with r0 =3D struct pt_regs * + mov r0, sp + bl do_busfault + + @ execute the pending work, including reschedule + get_thread_info tsk + mov why, #0 + b ret_to_user_from_irq +ENDPROC(__busfault_entry) + +__usagefault_entry: + v7m_exception_entry + + @ + @ Invoke the Bus Fault handler + @ routine called with r0 =3D struct pt_regs * + mov r0, sp + bl do_usagefault + + @ execute the pending work, including reschedule + get_thread_info tsk + mov why, #0 + b ret_to_user_from_irq +ENDPROC(__usagefault_entry) + __pendsv_entry: v7m_exception_entry =20 @@ -138,10 +198,10 @@ ENTRY(vector_table) .long 0 @ 0 - Reset stack pointer .long __invalid_entry @ 1 - Reset .long __invalid_entry @ 2 - NMI - .long __invalid_entry @ 3 - HardFault - .long __invalid_entry @ 4 - MemManage - .long __invalid_entry @ 5 - BusFault - .long __invalid_entry @ 6 - UsageFault + .long __hardfault_entry @ 3 - HardFault + .long __memmanage_entry @ 4 - MemManage + .long __busfault_entry @ 5 - BusFault + .long __usagefault_entry @ 6 - UsageFault .long __invalid_entry @ 7 - Reserved .long __invalid_entry @ 8 - Reserved .long __invalid_entry @ 9 - Reserved diff --git a/arch/arm/kernel/traps-v7m.c b/arch/arm/kernel/traps-v7m.c new file mode 100644 index 000000000000..5fd9943448e9 --- /dev/null +++ b/arch/arm/kernel/traps-v7m.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2011 Dmitry Cherukhin, Emcraft Systems + * Copyright (C) 2022 Ben Wolsieffer, Hefring Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include +#include +#include +#include + +enum fault { + FAULT_HARDFALT =3D 3, + FAULT_MEMMANAGE =3D 4, + FAULT_BUSFAULT =3D 5, + FAULT_USAGEFAULT =3D 6 +}; + +struct exception { + const char *name; + int fault; + int test_bit; + int signo; + int si_code; + unsigned int user_debug; +}; + +static const struct exception unknown_exception =3D + {"unknown exception", 0, 0, SIGSEGV, SEGV_MAPERR, UDBG_SEGV}; + +static const struct exception exceptions[] =3D { + {"escalated to hard fault", FAULT_HARDFALT, V7M_SCB_HFSR_FORCED, SIGSE= GV, SEGV_MAPERR, UDBG_SEGV}, + {"vector read error", FAULT_HARDFALT, V7M_SCB_HFSR_VECTTBL, SIGSEGV, = SEGV_MAPERR, UDBG_SEGV}, + {"divide by 0", FAULT_USAGEFAULT, V7M_SCB_CFSR_DIVBYZERO, SIGSEGV, SE= GV_MAPERR, UDBG_SEGV}, + {"illegal unaligned access", FAULT_USAGEFAULT, V7M_SCB_CFSR_UNALIGNED, = SIGBUS, BUS_ADRALN, UDBG_BUS}, + {"no coprocessor", FAULT_USAGEFAULT, V7M_SCB_CFSR_NOCP, SIGILL, ILL_C= OPROC, UDBG_UNDEFINED}, + {"return to invalid PC", FAULT_USAGEFAULT, V7M_SCB_CFSR_INVPC, SIGSEGV,= SEGV_MAPERR, UDBG_SEGV}, + {"invalid ISA state", FAULT_USAGEFAULT, V7M_SCB_CFSR_INVSTATE, SIGSEGV= , SEGV_MAPERR, UDBG_SEGV}, + {"undefined instruction", FAULT_USAGEFAULT, V7M_SCB_CFSR_UNDEFINSTR, SIG= ILL, ILL_ILLOPC, UDBG_UNDEFINED}, + {"floating point state error", FAULT_BUSFAULT, V7M_SCB_CFSR_LSPERR, SI= GBUS, BUS_ADRERR, UDBG_BUS}, + {"exception stack push error", FAULT_BUSFAULT, V7M_SCB_CFSR_STKERR, SI= GBUS, BUS_ADRERR, UDBG_BUS}, + {"exception stack pop error", FAULT_BUSFAULT, V7M_SCB_CFSR_UNSTKERR, S= IGBUS, BUS_ADRERR, UDBG_BUS}, + {"imprecise data bus error", FAULT_BUSFAULT, V7M_SCB_CFSR_IMPRECISERR, = SIGBUS, BUS_ADRERR, UDBG_BUS}, + {"precise data bus error", FAULT_BUSFAULT, V7M_SCB_CFSR_PRECISERR, SIG= BUS, BUS_ADRERR, UDBG_BUS}, + {"pre-fetch error", FAULT_BUSFAULT, V7M_SCB_CFSR_IBUSERR, SIGBUS, BU= S_ADRERR, UDBG_BUS}, + {"floating point state error", FAULT_MEMMANAGE, V7M_SCB_CFSR_MLSPERR, S= IGSEGV, SEGV_MAPERR, UDBG_SEGV}, + {"exception stack push error", FAULT_MEMMANAGE, V7M_SCB_CFSR_MSTKERR, S= IGSEGV, SEGV_MAPERR, UDBG_SEGV}, + {"exception stack pop error", FAULT_MEMMANAGE, V7M_SCB_CFSR_MUNSTKERR, = SIGSEGV, SEGV_MAPERR, UDBG_SEGV}, + {"data access violation", FAULT_MEMMANAGE, V7M_SCB_CFSR_DACCVIOL, SIGSE= GV, SEGV_ACCERR, UDBG_SEGV}, + {"instruction access violation", FAULT_MEMMANAGE, V7M_SCB_CFSR_IACCVIOL, = SIGSEGV, SEGV_ACCERR, UDBG_SEGV}, + {NULL} +}; + +/* + * Common routine for high-level exception handlers. + * @param regs state of registers when the exception occurs + * @param fault IPSR, the fault number + */ +static void traps_v7m_common(struct pt_regs *regs, int fault) +{ + unsigned long status; + unsigned long hstatus; + unsigned long cstatus; + unsigned long addr; + size_t i; + const struct exception *exc =3D &unknown_exception; + + + hstatus =3D readl(BASEADDR_V7M_SCB + V7M_SCB_HFSR); + cstatus =3D readl(BASEADDR_V7M_SCB + V7M_SCB_CFSR); + + if (cstatus & V7M_SCB_CFSR_MMARVALID && (fault =3D=3D FAULT_MEMMANAGE || + (fault =3D=3D FAULT_HARDFALT && hstatus & V7M_SCB_HFSR_FORCED))) { + addr =3D readl(BASEADDR_V7M_SCB + V7M_SCB_MMAR); + } else if (cstatus & V7M_SCB_CFSR_BFARVALID && (fault =3D=3D FAULT_BUSFAU= LT || + (fault =3D=3D FAULT_HARDFALT && hstatus & V7M_SCB_HFSR_FORCED))) { + addr =3D readl(BASEADDR_V7M_SCB + V7M_SCB_BFAR); + } else { + addr =3D instruction_pointer(regs); + } + + writel(hstatus, BASEADDR_V7M_SCB + V7M_SCB_HFSR); + writel(cstatus, BASEADDR_V7M_SCB + V7M_SCB_CFSR); + + for (i =3D 0; exceptions[i].name !=3D NULL; ++i) { + if (fault !=3D exceptions[i].fault) + continue; + + status =3D fault =3D=3D FAULT_HARDFALT ? hstatus : cstatus; + if (!(status & exceptions[i].test_bit)) + continue; + + exc =3D &exceptions[i]; + break; + } + +#ifdef CONFIG_DEBUG_USER + if (user_mode(regs) && (user_debug & exc->user_debug)) { + pr_info("%s (%d): %s: addr=3D0x%px\n", + current->comm, task_pid_nr(current), exc->name, (void *)addr); + __show_regs(regs); + } +#endif + + arm_notify_die(exc->name, regs, exc->signo, exc->si_code, + (void __user *)addr, 0, fault); +} + +/* + * High-level exception handler for exception 3 (Hard Fault). + * @param regs state of registers when the exception occurred + */ +asmlinkage void do_hardfault(struct pt_regs *regs) +{ + traps_v7m_common(regs, FAULT_HARDFALT); +} + +/* + * High-level exception handler for exception 4 (Mem Manage). + * @param regs state of registers when the exception occurred + */ +asmlinkage void do_memmanage(struct pt_regs *regs) +{ + traps_v7m_common(regs, FAULT_MEMMANAGE); +} + +/* + * High-level exception handler for exception 5 (Bus Fault). + * @param regs state of registers when the exception occurred + */ +asmlinkage void do_busfault(struct pt_regs *regs) +{ + traps_v7m_common(regs, FAULT_BUSFAULT); +} + +/* + * High-level exception handler for exception 6 (Usage Fault). + * @param regs state of registers when the exception occurred + */ +asmlinkage void do_usagefault(struct pt_regs *regs) +{ + traps_v7m_common(regs, FAULT_USAGEFAULT); +} --=20 2.38.1 From nobody Thu Sep 18 04:03:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3F27C4332F for ; Fri, 9 Dec 2022 21:54:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230046AbiLIVy1 (ORCPT ); Fri, 9 Dec 2022 16:54:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229981AbiLIVyW (ORCPT ); Fri, 9 Dec 2022 16:54:22 -0500 Received: from mail-qt1-x833.google.com (mail-qt1-x833.google.com [IPv6:2607:f8b0:4864:20::833]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EEFB275D2 for ; Fri, 9 Dec 2022 13:54:20 -0800 (PST) Received: by mail-qt1-x833.google.com with SMTP id x28so4689861qtv.13 for ; Fri, 09 Dec 2022 13:54:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FtMrmlc95PnCcPVYPyv6AphCDyoFhdBGfMeU1wU5s+s=; b=dnPGm+Ea6IJzbYga/myO6yYgHn0eOdbGEIM4N0FIXXIKzApv8en5HLVSziFmlqe5oy xNmzQAxW83hQ10+srOm/83LgF0a1KiWagRfyCSNMTzTW+RSj0QfowpqSgYOyS1Obk+mM 1+9buMHZE1n+k+XCUbCf2holRLYGfGLZsl7jxPLKUi8GVtg2OCZDn4Y3KbKN3Y1zroBg yhLHIg55cDs7zQ120c7WTKI3jaVfhciCTZNfPlJZnfMernXFwerbeOI2Fg7wVOpE6uWx UhQ600Ii8hzrRwVgvsVHTHlKnVvLdkmaX5rbt4dkrFrIGWwCEsg2/F75X8l5s56zeWaw ydkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FtMrmlc95PnCcPVYPyv6AphCDyoFhdBGfMeU1wU5s+s=; b=3ZDRzkujORXROJyYHSEs4JICACbkVXcFPQO8CDOWz18i2M/ChOFxzQ0jIPNnxXboL2 k09j8yY8uwbNhnCuRv0k7ItodN/eLHbKkKuZjaqd9TJVdHUtl53aYjVwmOPnDZa8+Edz 78RuVAHiWUdCEnfhaLo9lx4hanzbkw8nCkQQnAax7wdf5uPcVdzLf6IxdMpDOsI0A128 5TIgTeVqa2e5yAXAHau235juWtW2GFmS1O9ubZ5oZsSUxCqKCOYkzfiunWvJe7YV+WPL bYunoWVmAVb5y4PU377lXIEmKSL9IpQATg6Z5R1Wtm9XIvk5affBdr+PdfvCLnjOtuc+ jlrQ== X-Gm-Message-State: ANoB5pmznbo4xREPI+O4ZstVcgLTkEzl3FqryCqsqQsD1vpveLCZ1XbI VRhcXC0Vlho6DREGFOzZxgI= X-Google-Smtp-Source: AA0mqf5yU1rF1S/0Ku2uEBfm3PaqSjKArEAu/l8197FIy40qUKmMLAMi4jAE6ymNd0Kmmm/MAJ6aHA== X-Received: by 2002:a05:622a:488c:b0:3a7:ed31:a618 with SMTP id fc12-20020a05622a488c00b003a7ed31a618mr11349946qtb.7.1670622859382; Fri, 09 Dec 2022 13:54:19 -0800 (PST) Received: from Dell-Inspiron-15.. ([2601:18c:8380:74b0:e8e5:f40c:d741:8f07]) by smtp.gmail.com with ESMTPSA id p16-20020a05620a057000b006fee9a70343sm712718qkp.14.2022.12.09.13.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 13:54:18 -0800 (PST) From: Ben Wolsieffer To: linux-stm32@st-md-mailman.stormreply.com Cc: Linus Walleij , Ben Wolsieffer , Russell King , Ard Biesheuvel , "Russell King (Oracle)" , Arnd Bergmann , Catalin Marinas , Nicolas Schier , Masahiro Yamada , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 2/2] ARM: v7m: support undefined instruction hooks Date: Fri, 9 Dec 2022 16:48:13 -0500 Message-Id: <20221209214824.3444954-3-benwolsieffer@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209214824.3444954-1-benwolsieffer@gmail.com> References: <20221209214824.3444954-1-benwolsieffer@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Call the common ARM undefined instruction handler, which handles running hooks to enable ptrace breakpoints and other features. Signed-off-by: Ben Wolsieffer --- arch/arm/include/asm/traps.h | 2 ++ arch/arm/kernel/traps-v7m.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h index 987fefb0a4db..e4253f4a86e1 100644 --- a/arch/arm/include/asm/traps.h +++ b/arch/arm/include/asm/traps.h @@ -19,6 +19,8 @@ struct undef_hook { void register_undef_hook(struct undef_hook *hook); void unregister_undef_hook(struct undef_hook *hook); =20 +void do_undefinstr(struct pt_regs *regs); + static inline int __in_irqentry_text(unsigned long ptr) { extern char __irqentry_text_start[]; diff --git a/arch/arm/kernel/traps-v7m.c b/arch/arm/kernel/traps-v7m.c index 5fd9943448e9..b324499e1010 100644 --- a/arch/arm/kernel/traps-v7m.c +++ b/arch/arm/kernel/traps-v7m.c @@ -20,6 +20,7 @@ #include #include #include +#include #include =20 enum fault { @@ -49,7 +50,6 @@ static const struct exception exceptions[] =3D { {"no coprocessor", FAULT_USAGEFAULT, V7M_SCB_CFSR_NOCP, SIGILL, ILL_C= OPROC, UDBG_UNDEFINED}, {"return to invalid PC", FAULT_USAGEFAULT, V7M_SCB_CFSR_INVPC, SIGSEGV,= SEGV_MAPERR, UDBG_SEGV}, {"invalid ISA state", FAULT_USAGEFAULT, V7M_SCB_CFSR_INVSTATE, SIGSEGV= , SEGV_MAPERR, UDBG_SEGV}, - {"undefined instruction", FAULT_USAGEFAULT, V7M_SCB_CFSR_UNDEFINSTR, SIG= ILL, ILL_ILLOPC, UDBG_UNDEFINED}, {"floating point state error", FAULT_BUSFAULT, V7M_SCB_CFSR_LSPERR, SI= GBUS, BUS_ADRERR, UDBG_BUS}, {"exception stack push error", FAULT_BUSFAULT, V7M_SCB_CFSR_STKERR, SI= GBUS, BUS_ADRERR, UDBG_BUS}, {"exception stack pop error", FAULT_BUSFAULT, V7M_SCB_CFSR_UNSTKERR, S= IGBUS, BUS_ADRERR, UDBG_BUS}, @@ -95,6 +95,12 @@ static void traps_v7m_common(struct pt_regs *regs, int f= ault) writel(hstatus, BASEADDR_V7M_SCB + V7M_SCB_HFSR); writel(cstatus, BASEADDR_V7M_SCB + V7M_SCB_CFSR); =20 + if (fault =3D=3D FAULT_USAGEFAULT && cstatus & V7M_SCB_CFSR_UNDEFINSTR) { + /* Handle undefined instruction hooks */ + do_undefinstr(regs); + return; + } + for (i =3D 0; exceptions[i].name !=3D NULL; ++i) { if (fault !=3D exceptions[i].fault) continue; --=20 2.38.1