From nobody Thu Sep 18 07:23:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3553C4332F for ; Fri, 9 Dec 2022 10:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229900AbiLIKZy (ORCPT ); Fri, 9 Dec 2022 05:25:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229498AbiLIKZr (ORCPT ); Fri, 9 Dec 2022 05:25:47 -0500 Received: from mail-m121145.qiye.163.com (mail-m121145.qiye.163.com [115.236.121.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 599546ACC3; Fri, 9 Dec 2022 02:25:45 -0800 (PST) Received: from amadeus-VLT-WX0.lan (unknown [218.85.118.194]) by mail-m121145.qiye.163.com (Hmail) with ESMTPA id 03935800118; Fri, 9 Dec 2022 18:25:35 +0800 (CST) From: Chukun Pan To: Heiko Stuebner Cc: FUKAUMI Naoki , Peter Geis , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chukun Pan Subject: [PATCH v2 1/2] dt-bindings: arm: rockchip: add Radxa CM3I E25 Date: Fri, 9 Dec 2022 18:25:23 +0800 Message-Id: <20221209102524.129367-2-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221209102524.129367-1-amadeus@jmu.edu.cn> References: <20221209102524.129367-1-amadeus@jmu.edu.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCT00eVk9NShhCGEgZT0tOTFUTARMWGhIXJBQOD1 lXWRgSC1lBWUlKQ1VDTlVKSkNVSkJPWVdZFhoPEhUdFFlBWU9LSFVKSktISkNVSktLVUtZBg++ X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MiI6Kxw*Cz0sLEsrNUMWIzkw KkhPCytVSlVKTUxLTkNKTkhNTkJKVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUlK Q1VDTlVKSkNVSkJPWVdZCAFZQUlISEM3Bg++ X-HM-Tid: 0a84f66b45ccb03akuuu03935800118 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Radxa CM3 Industrial (CM3I) is an System on Module made by Radxa based on the Rockchip RK3568 SoC. The first carrier board supported is the Radxa E25. Add devicetree binding documentation for it. Signed-off-by: Chukun Pan Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 88ff4422a8c1..3af95dbb95dc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -599,6 +599,13 @@ properties: - const: pine64,soquartz - const: rockchip,rk3566 =20 + - description: Radxa CM3 Industrial + items: + - enum: + - radxa,e25 + - const: radxa,cm3i + - const: rockchip,rk3568 + - description: Radxa Rock items: - const: radxa,rock --=20 2.25.1 From nobody Thu Sep 18 07:23:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EDB5C4332F for ; Fri, 9 Dec 2022 10:25:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229929AbiLIKZ6 (ORCPT ); Fri, 9 Dec 2022 05:25:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229845AbiLIKZs (ORCPT ); Fri, 9 Dec 2022 05:25:48 -0500 Received: from mail-m121145.qiye.163.com (mail-m121145.qiye.163.com [115.236.121.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59B4A6ACD9; Fri, 9 Dec 2022 02:25:45 -0800 (PST) Received: from amadeus-VLT-WX0.lan (unknown [218.85.118.194]) by mail-m121145.qiye.163.com (Hmail) with ESMTPA id A002080011A; Fri, 9 Dec 2022 18:25:36 +0800 (CST) From: Chukun Pan To: Heiko Stuebner Cc: FUKAUMI Naoki , Peter Geis , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chukun Pan Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa CM3I E25 Date: Fri, 9 Dec 2022 18:25:24 +0800 Message-Id: <20221209102524.129367-3-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221209102524.129367-1-amadeus@jmu.edu.cn> References: <20221209102524.129367-1-amadeus@jmu.edu.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGkpIVkoeH0sYSB1JQ0lCTlUTARMWGhIXJBQOD1 lXWRgSC1lBWUlKQ1VDTlVKSkNVSkJPWVdZFhoPEhUdFFlBWU9LSFVKSktPS0NVSktLVUtZBg++ X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ogg6Izo6Lj0hDksyTEIvIzhL LwlPCjFVSlVKTUxLTkNKTkhMTUpMVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUlK Q1VDTlVKSkNVSkJPWVdZCAFZQUpMQ0JDNwY+ X-HM-Tid: 0a84f66b4841b03akuuua002080011a Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Radxa E25 is a network application carrier board for the Radxa CM3 Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC. It has the following features: - MicroSD card socket, on board eMMC flash - 2x 2.5GbE Realtek RTL8125B Ethernet transceiver - 1x USB Type-C port (Power and Serial console) - 1x USB 3.0 OTG port - mini PCIe socket (USB or PCIe) - ngff PCIe socket (USB or SATA) - 1x User LED and 16x RGB LEDs - 26-pin expansion header Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 416 ++++++++++++++++++ .../boot/dts/rockchip/rk3568-radxa-e25.dts | 229 ++++++++++ 3 files changed, 646 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 0a76a2ebb5f6..19dd314e425e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -81,4 +81,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-odroid-m1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi new file mode 100644 index 000000000000..225dbbe4955d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi @@ -0,0 +1,416 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model =3D "Radxa CM3 Industrial Board"; + compatible =3D "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc0 =3D &sdhci; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led_user: led-0 { + gpios =3D <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_HEARTBEAT; + color =3D ; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_user_en>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v_input>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v_input>; + }; + + /* labeled +5v_input in schematic */ + vcc5v_input: vcc5v-input-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v_input"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; +}; + +&combphy0 { + status =3D "okay"; +}; + +&combphy1 { + status =3D "okay"; +}; + +&combphy2 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&display_subsystem { + status =3D "disabled"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v_input>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_1v8>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb_host0_xhci { + extcon =3D <&usb2phy0>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64= /boot/dts/rockchip/rk3568-radxa-e25.dts new file mode 100644 index 000000000000..fb96019b0e87 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3568-radxa-cm3i.dtsi" + +/ { + model =3D "Radxa E25"; + compatible =3D "radxa,e25", "rockchip,rk3568"; + + aliases { + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + }; + + pwm-leds { + compatible =3D "pwm-leds-multicolor"; + + multi-led { + color =3D ; + max-brightness =3D <255>; + + led-red { + color =3D ; + pwms =3D <&pwm1 0 1000000 0>; + }; + + led-green { + color =3D ; + pwms =3D <&pwm2 0 1000000 0>; + }; + + led-blue { + color =3D ; + pwms =3D <&pwm12 0 1000000 0>; + }; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vbus_typec_en>; + regulator-name =3D "vbus_typec"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&minipcie_enable_h>; + regulator-name =3D "vcc3v3_minipcie"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ngffpcie_enable_h>; + regulator-name =3D "vcc3v3_ngff"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ + vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie30x1_enable_h>; + regulator-name =3D "vcc3v3_pcie30x1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_pi6c_05>; + }; + + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_enable_h>; + regulator-name =3D "vcc3v3_pcie"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&pcie2x1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie20_reset_h>; + reset-gpios =3D <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; +}; + +&pcie30phy { + data-lanes =3D <1 2>; + status =3D "okay"; +}; + +&pcie3x1 { + num-lanes =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie30x1m0_pins>; + reset-gpios =3D <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30x1>; + status =3D "okay"; +}; + +&pcie3x2 { + num-lanes =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie30x2_reset_h>; + reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; +}; + +&pinctrl { + pcie { + pcie20_reset_h: pcie20-reset-h { + rockchip,pins =3D <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_enable_h: pcie30x1-enable-h { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_reset_h: pcie30x2-reset-h { + rockchip,pins =3D <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_enable_h: pcie-enable-h { + rockchip,pins =3D <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + minipcie_enable_h: minipcie-enable-h { + rockchip,pins =3D <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ngffpcie_enable_h: ngffpcie-enable-h { + rockchip,pins =3D <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus_typec_en: vbus_typec_en { + rockchip,pins =3D <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status =3D "okay"; +}; + +&pwm2 { + status =3D "okay"; +}; + +&pwm12 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm12m1_pins>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + /* Also used in pcie30x1_clkreqnm0 */ + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vbus_typec>; + status =3D "okay"; +}; + +&usb2phy1_host { + phy-supply =3D <&vcc3v3_minipcie>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc3v3_ngff>; + status =3D "okay"; +}; --=20 2.25.1