From nobody Sat Sep 21 09:55:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7145C4332F for ; Fri, 9 Dec 2022 06:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229909AbiLIGpF (ORCPT ); Fri, 9 Dec 2022 01:45:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229939AbiLIGoe (ORCPT ); Fri, 9 Dec 2022 01:44:34 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70E71A0FA0; Thu, 8 Dec 2022 22:44:23 -0800 (PST) X-UUID: a4655d34303d4e2798627ba09a85d193-20221209 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=v0RLYJNNjOaZwIF3K4Tu0NmZq0XJJx6TB5aHEi73l4Y=; b=Ht7fPbYOSUzkOgyShnePQKa+3GOW23lHgFJzQezBJ91zhjtF934Fabxchw3oh1+Bqv854HNB9uywchl2k28swfeEMftcPdWxJidm0Mh9yD/k9k/UJ2tMU6Pemo/fj8slfQrYIsnKAlIfgJ9eHYHn2lAW0SmyTfYv+BKzJyLZcHM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:132f3510-5d59-4fd9-be16-f6b003fd7c76,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.14,REQID:132f3510-5d59-4fd9-be16-f6b003fd7c76,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:dcaaed0,CLOUDID:2f1c1bd2-652d-43fd-a13a-a5dd3c69a43d,B ulkID:221208143012S7AUV1SI,BulkQuantity:8,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:41,QS:nil,BEC:nil,COL:0 X-UUID: a4655d34303d4e2798627ba09a85d193-20221209 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1178571859; Fri, 09 Dec 2022 14:44:17 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 9 Dec 2022 14:44:15 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 9 Dec 2022 14:44:15 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , , "AngeloGioacchino Del Regno" Subject: [PATCH v4 5/9] spi: mtk-snfi: Add snfi sample delay and read latency adjustment Date: Fri, 9 Dec 2022 14:43:13 +0800 Message-ID: <20221209064317.2828-6-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221209064317.2828-1-xiangsheng.hou@mediatek.com> References: <20221209064317.2828-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add snfi sample delay and read latency adjustment which can get from dts property. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 85644308df23..f3f95eb37365 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -195,6 +195,8 @@ #define DATA_READ_MODE_X4 2 #define DATA_READ_MODE_DUAL 5 #define DATA_READ_MODE_QUAD 6 +#define DATA_READ_LATCH_LAT GENMASK(9, 8) +#define DATA_READ_LATCH_LAT_S 8 #define PG_LOAD_CUSTOM_EN BIT(7) #define DATARD_CUSTOM_EN BIT(6) #define CS_DESELECT_CYC_S 0 @@ -205,6 +207,9 @@ =20 #define SNF_DLY_CTL3 0x548 #define SFCK_SAM_DLY_S 0 +#define SFCK_SAM_DLY GENMASK(5, 0) +#define SFCK_SAM_DLY_TOTAL 9 +#define SFCK_SAM_DLY_RANGE 47 =20 #define SNF_STA_CTL1 0x550 #define CUS_PG_DONE BIT(28) @@ -1368,6 +1373,8 @@ static int mtk_snand_probe(struct platform_device *pd= ev) const struct of_device_id *dev_id; struct spi_controller *ctlr; struct mtk_snand *ms; + unsigned long spi_freq; + u32 val =3D 0; int ret; =20 dev_id =3D of_match_node(mtk_snand_ids, np); @@ -1446,6 +1453,19 @@ static int mtk_snand_probe(struct platform_device *p= dev) // switch to SNFI mode nfi_write32(ms, SNF_CFG, SPI_MODE); =20 + ret =3D of_property_read_u32(np, "rx-sample-delay-ns", &val); + if (!ret) + nfi_rmw32(ms, SNF_DLY_CTL3, SFCK_SAM_DLY, + val * SFCK_SAM_DLY_RANGE / SFCK_SAM_DLY_TOTAL); + + ret =3D of_property_read_u32(np, "mediatek,rx-latch-latency-ns", &val); + if (!ret) { + spi_freq =3D clk_get_rate(ms->pad_clk); + val =3D DIV_ROUND_CLOSEST(val, NSEC_PER_SEC / spi_freq); + nfi_rmw32(ms, SNF_MISC_CTL, DATA_READ_LATCH_LAT, + val << DATA_READ_LATCH_LAT_S); + } + // setup an initial page format for ops matching page_cache_op template // before ECC is called. ret =3D mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64); --=20 2.25.1