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[2a02:8388:6582:fe80::7]) by smtp.gmail.com with ESMTPSA id a6-20020adfed06000000b0028e8693bb75sm1887655wro.63.2022.12.29.23.42.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 23:42:29 -0800 (PST) From: Luca Weiss Date: Fri, 30 Dec 2022 08:42:07 +0100 Subject: [PATCH v2 3/3] dt-bindings: ufs: qcom: Fix sm8450 bindings MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221209-dt-binding-ufs-v2-3-dc7a04699579@fairphone.com> References: <20221209-dt-binding-ufs-v2-0-dc7a04699579@fairphone.com> In-Reply-To: <20221209-dt-binding-ufs-v2-0-dc7a04699579@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Iskren Chernev Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.11.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8450 actually supports ICE (Inline Crypto Engine) so adjust the bindings and the example to match. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index a8d896e1617b..2f73a84fcf41 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -107,7 +107,6 @@ allOf: - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - - qcom,sm8450-ufshc then: properties: clocks: @@ -137,6 +136,7 @@ allOf: - qcom,sdm845-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc + - qcom,sm8450-ufshc then: properties: clocks: @@ -243,7 +243,9 @@ examples: ufs@1d84000 { compatible =3D "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0 0x01d84000 0 0x3000>; + reg =3D <0 0x01d84000 0 0x3000>, + <0 0x01d88000 0 0x8000>; + reg-names =3D "std", "ice"; interrupts =3D ; phys =3D <&ufs_mem_phy_lanes>; phy-names =3D "ufsphy"; @@ -271,7 +273,8 @@ examples: "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; + "rx_lane1_sync_clk", + "ice_core_clk"; clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -279,7 +282,8 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; freq-table-hz =3D <75000000 300000000>, <0 0>, <0 0>, @@ -287,6 +291,7 @@ examples: <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; }; }; --=20 2.39.0