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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id h10-20020a5d504a000000b002366553eca7sm10673239wrt.83.2022.12.08.07.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:30:43 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v4 1/7] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board Date: Thu, 8 Dec 2022 16:30:34 +0100 Message-Id: <20221208153041.3965378-2-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208153041.3965378-1-bero@baylibre.com> References: <20221208153041.3965378-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for the Mediatek mt8365-evk board. Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 2275e5d93721b..ae12b1cab9fbd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -244,6 +244,10 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek,mt8365 - items: - enum: - mediatek,mt8516-pumpkin --=20 2.38.1 From nobody Sat Sep 21 07:50:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4426C3A5A7 for ; Thu, 8 Dec 2022 15:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229902AbiLHPcO (ORCPT ); Thu, 8 Dec 2022 10:32:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbiLHPaw (ORCPT ); Thu, 8 Dec 2022 10:30:52 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED64484B76 for ; Thu, 8 Dec 2022 07:30:45 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id h10so2040631wrx.3 for ; Thu, 08 Dec 2022 07:30:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4YM8esfRUJI66AUcHAfU4GRcLBt7unfApTHLgo4eQjI=; b=pie0o9goXLxTxFDA4wcDy1QkVwL1bOKcv7mDRQAf3WeuYm3BAAAlDpu+FU0MBZcybk k8avyESThu3slr+rgSsV6dR1RvPy7V06I8Vm49srfp6xJvvo1CeRz8+RqyjgFVkq8fGv Lt8X3emhtDcbXvkbErRRYlG4gW4rF0WUKg992gH677fkHXcsCAiGWjNyd4Sa0N1pSAfb J1K/Ul2U+sU1MLlcXBjkDWdzoYHC6AQitcuixVlM2fhkfLJ1fOC0pl9gM9mZOmeFVW2z KwEk9Wm1bPMZNqLGSK5Uthq9wxcSRzsp4kRWXWUA02ehd0GpA49xJn+TY2jhJ0txBh7N /teQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4YM8esfRUJI66AUcHAfU4GRcLBt7unfApTHLgo4eQjI=; b=uRzxNXQUHmKwGapY5M8PTP1qHIUNsFy3ngHoObCq+cQSnJf7DADWfZcFUiK2XePSOe tlaJg2K2XBkiBkJ/tgpXte3oNJS5vtAx6H9UmRs5fXFcdwmQHbXyO7H3h+15ySvMl8ac J0e5/hUzfdIMMBnejunIQxa1BUejtKSXho7One38Y2/pNE7bNPFq5CEA6ZiQphLsNmQM mR1tOKyvx5QLLtbAbDA32wOt6pFa4fELxSuhIqbh1HwN0VxqN2rWlg+8DeXUnp/pZC8w wAVxUipm/VDcdw+v4x7M/EC7GNB2FUh4UPglGfdi07fM/zNyMUZrJQ0koAEcioGM9wEU hAAQ== X-Gm-Message-State: ANoB5pmsAjMKfoAQGndzvDeswyaTa/pBdCSv9m03cVE+DRILQTNeoD1a LvfNpdCPvK0gvAT24iGHNViVbQ== X-Google-Smtp-Source: AA0mqf6GZP9OH5wdGjbihY7E5o2kNENG7XJO2LlCOF0ySSKsJ5o9aJAkw7mGbagi4uWcljWa5J/rOw== X-Received: by 2002:a05:6000:1d84:b0:236:3686:797 with SMTP id bk4-20020a0560001d8400b0023636860797mr1652958wrb.65.1670513444313; Thu, 08 Dec 2022 07:30:44 -0800 (PST) Received: from predatorhelios.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h10-20020a5d504a000000b002366553eca7sm10673239wrt.83.2022.12.08.07.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:30:43 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v4 2/7] dt-bindings: irq: mtk, sysirq: add support for mt8365 Date: Thu, 8 Dec 2022 16:30:35 +0100 Message-Id: <20221208153041.3965378-3-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208153041.3965378-1-bero@baylibre.com> References: <20221208153041.3965378-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding documentation of mediatek,sysirq for mt8365 SoC. Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediate= k,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/media= tek,sysirq.txt index 84ced3f4179b9..3ffc60184e445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysir= q.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysir= q.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.tx= t. - reg: Physical base address of the intpol registers and length of memory --=20 2.38.1 From nobody Sat Sep 21 07:50:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF71FC4332F for ; Thu, 8 Dec 2022 15:32:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230408AbiLHPc0 (ORCPT ); Thu, 8 Dec 2022 10:32:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229835AbiLHPax (ORCPT ); Thu, 8 Dec 2022 10:30:53 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FEA184B79 for ; Thu, 8 Dec 2022 07:30:46 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id m14so2031202wrh.7 for ; Thu, 08 Dec 2022 07:30:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q3nZeW09fXhVKKN3KyKLvbBj2rJc2M/wLUemiWl6Iqs=; b=YyB4q4SP2Ry2z6DrrRHmmwjWcPgRFwce6rxxmTxyykraQzc/9RkRP51FXEwHqZO7m/ 20wYbxkj8FWEHX88116T3WnWkCOFXqerpwf5iZ/n3l4lqcXnGpqP0AswXb6io8a3bJDE 0tYCR3oJ9z+1xzl7MFTvoXVgohGjqbKUq/Ubv4wvkgzmemfm1HWm1ElB7eujYVenf5eq SERSELje+miYCcp9/+8hwqMAcaGpx6ry8DXjpTMXfLqhCBMtoWjoSnItTH/Uf2rmethG iofiTxEVvRhzFkl0Kat1YIuNJwBEb1OCyu9ZInTMC1nJ/z8o0LxSnyyjw3R7nGYPc9uj Q4QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q3nZeW09fXhVKKN3KyKLvbBj2rJc2M/wLUemiWl6Iqs=; b=KzgRvbEYJTni8QWT616e8iMODe08/2cY76/QS6iBnL9bb5KgHbCC4v95MSIE9qMMTl 1iDCnargUXOg2dty/FWlCwFvuRLY5QW0I3Eexc+Au1jtmx5+8sFVveyhWWfh2msRJ2Pt 0wi4dMDt4M6sDktcmK3Ec2RdLBzNM2NEfpGOXsF4J9yszZq+gwpxhbtpLMpJbi6N10X/ z4/2l1/3zXuiOJOst1xFeV1NRdda1nWAnm5E+DJ70Ucj0mlzL1CFqlUPFFNWm8bB2wxh Nv/2eAyGHSZEfaohxy6c8soeVVO6OFGXpvFxfEeZWtcYSROTLLuNRtHHmPRKwtWB9yS7 v/Mw== X-Gm-Message-State: ANoB5pmmW/clBQn64VpUwWk8es9qV2PljRBvzSYqXDu4BR1lSn5AOb2K p3vubCCA30kDny8wz1q0OUYeoA== X-Google-Smtp-Source: AA0mqf7iR2EvjsGHr5MUa13qi18194p51dzW5Cj4dAGfA4boSpbwmRh+IGQ2kMfCSK6jzlU1UqxyFQ== X-Received: by 2002:a5d:58ea:0:b0:241:f85e:75ca with SMTP id f10-20020a5d58ea000000b00241f85e75camr1571723wrd.9.1670513445136; Thu, 08 Dec 2022 07:30:45 -0800 (PST) Received: from predatorhelios.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h10-20020a5d504a000000b002366553eca7sm10673239wrt.83.2022.12.08.07.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:30:44 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v4 3/7] dt-bindings: mfd: syscon: Add mt8365-syscfg Date: Thu, 8 Dec 2022 16:30:36 +0100 Message-Id: <20221208153041.3965378-4-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208153041.3965378-1-bero@baylibre.com> References: <20221208153041.3965378-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document Mediatek mt8365-syscfg Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 1b01bd0104316..7beeb0abc4db0 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -50,6 +50,7 @@ properties: - marvell,armada-3700-usb2-host-misc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep --=20 2.38.1 From nobody Sat Sep 21 07:50:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0CEFC3A5A7 for ; Thu, 8 Dec 2022 15:32:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230262AbiLHPcK (ORCPT ); Thu, 8 Dec 2022 10:32:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230384AbiLHPax (ORCPT ); Thu, 8 Dec 2022 10:30:53 -0500 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A65138C443 for ; Thu, 8 Dec 2022 07:30:47 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id bx10so2067538wrb.0 for ; Thu, 08 Dec 2022 07:30:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XmyXJeXOh9aIrCgjS6ftss8a4dPzBjoQogZkMKVqyWc=; b=hqrjX4JfWZoBrCAot0Pdqad0u+00X9VWJckZrhwVPufe+2y50mIxI6lywOceVZThj+ EMVQMeHYlXsdRurNXflgvx/2yY/K0z67n/5UmTyMsKnlyfPr20WuF0IBCL3kgVJMpSXM 4CspMocxDypnIzhQd3iUG6tyDySfWRuLsUrfalMhn3UR8FE+oOgwMcZG4n1JsbYdb6Tf hTR7MdGKQ1F19TSfBYlovRbvzqRATKkQ02qOpJPT3uV62wSxH7K0NHVm3Cd/z9HonmEA EyFBusJ/cT7pELthYlgxfBlvK7rOWgU3wIRdT9uKSPGqSwmb2mr1NKd9DsphUBjV4cIU pHgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XmyXJeXOh9aIrCgjS6ftss8a4dPzBjoQogZkMKVqyWc=; b=e4yTr5uqbYd/k6zYLGP+uCcyKawQO9BI+/VWwYkjJCUMO+icliz/QuYUQDfM9kHI/N V5SrCK4TX6MaJdCTj+Z3tBFTfyGWLvL/27YAw5kauMW6EcmByQ/ugE2ORPj5cxkkXS01 QHr5m/9ZkkuvXcCfsIaLjccDCFvu/7jYc/jnEeus4j9CTma6pZfYlLRvazEmncI2s/6T 7pnz83gUkbfQzK6l7K9uhWb722WZQXCms6faRJ8nsIEsAMdNA0vwRMzrru55Fs0zk8gk baGoSawdwWMoTMbzv49/F3NuBUyyhT23+0XvlaY2PrjWAULORBB54sLo9sa7//LQDI0M 0Jsg== X-Gm-Message-State: ANoB5pmVI5Wm0sPk7Ap0FzgvMRHniDVJSwETx07upkRqplRgxOMlreL9 hXGLKvyGc3/pIIKbofjjegOGGQ== X-Google-Smtp-Source: AA0mqf4WGrL7QmgPKiJfmGndgA7HOEsLEFGcRF2+/P6E7r6tgmdnm/eY825sb/6L3ogndviMGn7Zxw== X-Received: by 2002:a05:6000:11cf:b0:242:2e74:7930 with SMTP id i15-20020a05600011cf00b002422e747930mr1762192wrx.10.1670513445960; Thu, 08 Dec 2022 07:30:45 -0800 (PST) Received: from predatorhelios.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h10-20020a5d504a000000b002366553eca7sm10673239wrt.83.2022.12.08.07.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:30:45 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v4 4/7] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Date: Thu, 8 Dec 2022 16:30:37 +0100 Message-Id: <20221208153041.3965378-5-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208153041.3965378-1-bero@baylibre.com> References: <20221208153041.3965378-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt83= 65-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctr= l.yaml new file mode 100644 index 0000000000000..9560e1d2898d0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkr=C3=A4nzer + +description: |+ + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the= below + mentioned gpio binding representation for description of particular = cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + 'pins$': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing = the + pinctrl groups available on the machine. Each subnode will list = the + pins it needs, and how they should be configured, with regard to= muxer + configuration, pullups, drive strength, input enable/disable and= input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pul= l up + settings for 2 pull resistors, R0 and R1. User can configure= those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only su= pport + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup= , they + can support 0.125/0.25/0.5/1mA adjustment. If we enable spec= ific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=3D0/E0=3D0, the strength is 0.125mA. + When E1=3D0/E0=3D1, the strength is 0.25mA. + When E1=3D1/E0=3D0, the strength is 0.5mA. + When E1=3D1/E0=3D1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) =3D (0, 0, 0) + 1: (E1, E0, EN) =3D (0, 0, 1) + 2: (E1, E0, EN) =3D (0, 1, 0) + 3: (E1, E0, EN) =3D (0, 1, 1) + 4: (E1, E0, EN) =3D (1, 0, 0) + 5: (E1, E0, EN) =3D (1, 0, 1) + 6: (E1, E0, EN) =3D (1, 1, 0) + 7: (E1, E0, EN) =3D (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arg= uments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty= cycle + when asserted (high pulse width adjustment). Valid arguments= are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + pio-pins { + pins { + pinmux =3D , ; + mediatek,pull-up-adv =3D <3>; + mediatek,drive-strength-adv =3D <00>; + bias-pull-up; + }; + }; + }; + }; + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# --=20 2.38.1 From nobody Sat Sep 21 07:50:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 036A9C4332F for ; Thu, 8 Dec 2022 15:32:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230447AbiLHPcd (ORCPT ); Thu, 8 Dec 2022 10:32:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230386AbiLHPay (ORCPT ); Thu, 8 Dec 2022 10:30:54 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D15198E86 for ; Thu, 8 Dec 2022 07:30:48 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id h12so2020173wrv.10 for ; Thu, 08 Dec 2022 07:30:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xDJr0JNgTCOMxRZclskMbEi5U/4ZKMcH67crmF1PMpE=; b=Mt3jE+le0MGXv1iAIXnoBBkc8fokd+3aEZfOC8Y5+nYh4svi/5AdVqugjdtnDHx/Ji kOFhOEUJZpWyWlDMjzMNKuBXk9tFLiGhJXuToi277b2mLN0wbceaZag4n8+WGDOR0TFd bTNIhnQsyP59x0v9Dt7Pvgf1U+hUNg+CgO7ystvtFnZJSGn2MgKYOZy9qLt8Zr/gPzut Aw85CksnFGjOYp+imRxuPsXUEH7T5CMiAlf3bzsuR2GVdow0V9V9WzCZIATGL8BFNs6U wxOzwpFBY4gwrY2cFdshm6gByS91YY/iEO8QOITzzmWd0lNs/vxeuWtC24fPrT9SptFQ Ms9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xDJr0JNgTCOMxRZclskMbEi5U/4ZKMcH67crmF1PMpE=; b=MMVjEmmHKc5jvEu03JTpDQZiqsv463JLXeQdEMDtpfGiFFbyTcXmPXpCv4i4uBSJvu i7bU0Sh45bNd00jgSVhqIwRzsmMSy0/tppLgtjaUimzMv7CVArmeTzKr35KeKuCWyjZu v5ATr4o1BpQxgYgT5redPecDh9NRh2FtATY9wKoK896npk7JznLZFe8D8mu/QelaaBZJ mJoUS6vYqEfMbYUoXL9sfbDDMaXkcKXDhy6OLcNzf7yeaMKmX5YuS50EQymi3sfkSZGC NYfkjvM8KHPRlLNEUqfQLd0IoF4A8THQNuBiWsYcH5el5ZWWKz4QUw0+PQeRxeYWoHYI eSAw== X-Gm-Message-State: ANoB5pmhd4BEuKPzhHN9mJkxTCZvhqFwyA0TwQOmMeDQBNeVf367akgj Ohntyefx0RAaLA/RR5P0L7xCaw== X-Google-Smtp-Source: AA0mqf67lfHIJwHfsORr5HkhkFVrVxVhlkCojfRkbwd4ml08Xz+iO8ncJ9VcfWf+AbAx+sSMtIcRRA== X-Received: by 2002:adf:efc8:0:b0:242:f3f:28df with SMTP id i8-20020adfefc8000000b002420f3f28dfmr1434570wrp.58.1670513446920; Thu, 08 Dec 2022 07:30:46 -0800 (PST) Received: from predatorhelios.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h10-20020a5d504a000000b002366553eca7sm10673239wrt.83.2022.12.08.07.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:30:46 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v4 5/7] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings Date: Thu, 8 Dec 2022 16:30:38 +0100 Message-Id: <20221208153041.3965378-6-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208153041.3965378-1-bero@baylibre.com> References: <20221208153041.3965378-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Doc= umentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 7168110e2f9de..d2655173e108c 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 =20 reg: --=20 2.38.1 From nobody Sat Sep 21 07:50:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7AB9C63703 for ; Thu, 8 Dec 2022 15:32:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229865AbiLHPcT (ORCPT ); Thu, 8 Dec 2022 10:32:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230392AbiLHPaz (ORCPT ); Thu, 8 Dec 2022 10:30:55 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BF3F84B7D for ; Thu, 8 Dec 2022 07:30:49 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id h12so2020216wrv.10 for ; Thu, 08 Dec 2022 07:30:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g6+ABKaCFT5+1C0Y5clbHMJQa6kjF8TIULfr4cCgl3o=; b=LCM7oOJmoRy3wGsCUMZoYwr4aV/73j1pYFhJO1iyfzfdj3blRZvKZ9A7suusfQN3IK HVhZRy+PL2X0cNNsC5KQp5DgCNKpAttJ396X3I4R8ldvQdKBGe3fJ1ik2epMa1x7tqao qDET9+GWyGzE+IFBrTufBYCQDV9QFNzm0R84bD3/QDUSfHpjgKHT6PileWavmSptJc2n 7vc/NwPAJQFmaeiZh1ightM1l2fYFyRF4SPdvA2O63R1QabasL939xMxgR1e7hDJHTII xZ5a8x3tumNJhtq92nPdzh9DyWPqH3fQ6puB38waQgqaZOWPPFmBcfhremrScaTkRTS3 4BnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g6+ABKaCFT5+1C0Y5clbHMJQa6kjF8TIULfr4cCgl3o=; b=xCZqAQvr21id62AlIu28WqEqAtk3qba22ikAwdUOFwQ572PI1ZaA3XnzlGUZ1DyVMT S+Ck8JcD0/m64M5a91rKul+O55EhxDRX9nEtkSx3FcHRQaWyO75hynmgLKa9m5K+5Vfe HQpiFIusSmkSLN438QZJsH9xHH05/vJiDGfMXZSjumMD/X+XwewzEA5nKALxU2pp5hhr q6cJbEg4Uf20C09l8zYtkVXcrSqbrrqhostnDvSwZbZoYAnVXjLbGVXlItUjb9jWGO60 XhHEyBQa82DnO6qTzn5Eq9z64Pekm8O3ZYV4C+gap2TifozNU/dTQGqNHd0b0/V4ScSx Eorg== X-Gm-Message-State: ANoB5pnNDJYAN6PrCwwoGL1Nr9uCgyljoiJGvL/CKAXVUatpFudcgoEt jGCAmvxBtljY8w9F/mWB6LaWMg== X-Google-Smtp-Source: AA0mqf5FOPXltuZLPneEbB5VngzDKQGwN6thrtAgUY/6DvNUrqLQncoLNWjNWmFSiUbzrk74ARetEQ== X-Received: by 2002:a5d:6407:0:b0:242:2cb4:6fa2 with SMTP id z7-20020a5d6407000000b002422cb46fa2mr1703001wru.31.1670513447701; Thu, 08 Dec 2022 07:30:47 -0800 (PST) Received: from predatorhelios.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h10-20020a5d504a000000b002366553eca7sm10673239wrt.83.2022.12.08.07.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:30:47 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v4 6/7] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings Date: Thu, 8 Dec 2022 16:30:39 +0100 Message-Id: <20221208153041.3965378-7-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208153041.3965378-1-bero@baylibre.com> References: <20221208153041.3965378-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b= /Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 939623867a646..3b92725bbc99b 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci =20 reg: --=20 2.38.1 From nobody Sat Sep 21 07:50:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32EB5C4332F for ; Thu, 8 Dec 2022 15:32:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230382AbiLHPch (ORCPT ); Thu, 8 Dec 2022 10:32:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230395AbiLHPaz (ORCPT ); Thu, 8 Dec 2022 10:30:55 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F189A84B7E for ; Thu, 8 Dec 2022 07:30:50 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id q7so2028751wrr.8 for ; Thu, 08 Dec 2022 07:30:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4YLyMwQEX4j02r/KqUD6rHkcfDS7rxMx+5HAE0rPHaw=; b=UnJQ/5gApEW6S5dY3UG5wkd5kjCjf/0+NyK4VSrRes1jTiuAw33KTEnlsxligqckHg f6krJM5gnzoc/SHZtjBJK7azynPA8DZj5sE8oyf7dPmpbA+548YFMJFocWgvxBgVjSHw H/8L94eltIbiJrBdUnGmOgRCaI3/1umORFTkwaxUmBbJ5b4uDcZWZm/+nM6/PBarvZ1m y6wzZv8ASsL2JdzgxznhUAZ5apMo5kGvpaV4YJz/a+aAIYBy6dzV8IjbGLr3xtFZvtAj Xw6vL5aLbW4W+8IizRTfnMf0TFc4V3gZommcGrBFWOVaCP/kfSt/bRxUf0yHH2nZL42b Id0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4YLyMwQEX4j02r/KqUD6rHkcfDS7rxMx+5HAE0rPHaw=; b=RHt+rgXmRYTCfQSrWCRvdE8TtlyUVT9bCUXWdk5B3h6YfafgfcnoK39wQCtq73Et/K 327/mVxqYQ6YMN93thpt23mA0w17uvPYWxfpf7znjKfKJpkF5Pax5HEv+xSh6DSS32rV ExJkjOolf+q4O4cNcjubxepFay5eAkqk15wHOXBZy5N5CrC86XHtb9gDUohQJfbkUI4F C7qT1c1jQjU7qCX0fEyIhIKQCtW66jCyMVavQ1ZBFmIV0AhdPun+U8UIvfLPXUbIj5om ZCj4OfOdlUPnHAMZ4VX+3PLHTNX/lbqDPT9vIgTQLWRi83noj5nmU8ZtqtEW+/24Qr63 ohJw== X-Gm-Message-State: ANoB5pmvs61RU2zpDUggpJo8w6wv3HsAYRIMecelhUMkiOEl75YEcBx9 k99H9pwqOxdfZmAzDD/f4T7tGw== X-Google-Smtp-Source: AA0mqf6KctvlTIr8QP6xdoSI/eMzNaBzcauxDBwUvvWu3x7Ewak2XZr9o6a4Apc7X5pM2TV6rDkuVw== X-Received: by 2002:a05:6000:234:b0:242:29fc:ad51 with SMTP id l20-20020a056000023400b0024229fcad51mr1718605wrz.20.1670513448500; Thu, 08 Dec 2022 07:30:48 -0800 (PST) Received: from predatorhelios.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h10-20020a5d504a000000b002366553eca7sm10673239wrt.83.2022.12.08.07.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:30:48 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v4 7/7] arm64: dts: mediatek: Initial mt8365-evk support Date: Thu, 8 Dec 2022 16:30:40 +0100 Message-Id: <20221208153041.3965378-8-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208153041.3965378-1-bero@baylibre.com> References: <20221208153041.3965378-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream= yet, cleanups, add L2 cache] Signed-off-by: Bernhard Rosenkr=C3=A4nzer Tested-by: Kevin Hilman --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 163 ++++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 343 ++++++++++++++++++++ 3 files changed, 507 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 813e735c5b96d..d78523c5a7dd6 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r2.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts new file mode 100644 index 0000000000000..972843f9e4e9d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model =3D "MediaTek MT8365 Open Platform EVK"; + compatible =3D "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + input-name =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys>; + + key-volume-up { + gpios =3D <&pio 24 GPIO_ACTIVE_LOW>; + label =3D "volume_up"; + linux,code =3D ; + wakeup-source; + debounce-interval =3D <15>; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "otg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg =3D <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&pio { + gpio_keys: gpio-keys-pins { + pins { + pinmux =3D ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + }; + }; + + usb_pins: usb-pins { + pins-id { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-usb0-vbus { + pinmux =3D ; + output-high; + }; + + pin-usb1-vbus { + pinmux =3D ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux =3D , + ; + }; + }; +}; + +&pwm { + pinctrl-0 =3D <&pwm_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi new file mode 100644 index 0000000000000..2c4ef9b92b68b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8365"; + interrupt-parent =3D <&sysirq>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + }; + }; + + clk26m: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg =3D <0 0x43000000 0 0x20000>; + }; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x80000>, <0 0x0c080000 0 0x80000>; + + interrupts =3D ; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8365-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg: syscon@10001000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8365-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible =3D "mediatek,mt8365-syscfg", "syscon"; + reg =3D <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8365-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + keypad: keypad@10010000 { + compatible =3D "mediatek,mt6779-keypad"; + reg =3D <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts =3D ; + clocks =3D <&clk26m>; + clock-names =3D "kpd"; + status =3D "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible =3D "mediatek,mt8365-mcucfg", "syscon"; + reg =3D <0 0x10200000 0 0x2000>; + #clock-cells =3D <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible =3D "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&gic>; + reg =3D <0 0x10200a80 0 0x20>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x1020e000 0 0x1000>; + }; + + rng: rng@1020f000 { + compatible =3D "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg =3D <0 0x1020f000 0 0x100>; + clocks =3D <&infracfg CLK_IFR_TRNG>; + clock-names =3D "rng"; + }; + + apdma: dma-controller@11000280 { + compatible =3D "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg =3D <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts =3D , + , + , + , + , + ; + dma-requests =3D <6>; + clocks =3D <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "apdma"; + #dma-cells =3D <1>; + }; + + uart0: serial@11002000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 0>, <&apdma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart1: serial@11003000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 2>, <&apdma 3>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart2: serial@11004000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11004000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 4>, <&apdma 5>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + pwm: pwm@11006000 { + compatible =3D "mediatek,mt8365-pwm"; + reg =3D <0 0x11006000 0 0x1000>; + #pwm-cells =3D <2>; + interrupts =3D ; + clocks =3D <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names =3D "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + spi: spi@1100a000 { + compatible =3D "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg =3D <0 0x1100a000 0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + ssusb: usb@11201000 { + compatible =3D "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host: usb@11200000 { + compatible =3D "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>; + reg-names =3D "mac"; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status =3D "disabled"; + }; + }; + + u3phy: phy@11cc0000 { + compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #size-cells =3D <2>; + #phy-cells =3D <1>; + ranges; + + u2port0: usb-phy@11cc0000 { + reg =3D <0 0x11cc0000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + + u2port1: usb-phy@11cc1000 { + reg =3D <0 0x11cc1000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.38.1