From nobody Sat Sep 21 09:35:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FD3AC6370D for ; Thu, 8 Dec 2022 06:30:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229867AbiLHGaV (ORCPT ); Thu, 8 Dec 2022 01:30:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229819AbiLHGaP (ORCPT ); Thu, 8 Dec 2022 01:30:15 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C72DDD128; Wed, 7 Dec 2022 22:30:11 -0800 (PST) X-UUID: 2d09aaa1862045089e0d0dece6a1b119-20221208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FNzZA4Rvah6EiOVCThpkNxdRZy233GREfbroF6vG1AY=; b=f/uVs4RQPJyebFpZFkkDnmQUVUtOlPsYcwmnyt/tvrSarOTQ2ROfUtRff1pq9vduVgfoBPt4ZaZK6Ns6DaRPs2PkC0nUSnOc9pNF2l+EvWFD7KzcDi1jBl5lFV4/ImJSqAW4UVaehdb1KanQalgL5JYo2bMNqEKOumrkov8rk/M=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:90b90881-fe7a-415e-a5cd-adfa1d3ec907,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:90b90881-fe7a-415e-a5cd-adfa1d3ec907,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:72c9e416-b863-49f8-8228-cbdfeedd1fa4,B ulkID:221208143007N99SWYXQ,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 2d09aaa1862045089e0d0dece6a1b119-20221208 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1768016395; Thu, 08 Dec 2022 14:30:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 8 Dec 2022 14:30:03 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 8 Dec 2022 14:30:02 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , , "AngeloGioacchino Del Regno" Subject: [PATCH v3 2/9] spi: mtk-snfi: Add optional nfi_hclk which is needed for MT7986 Date: Thu, 8 Dec 2022 14:29:48 +0800 Message-ID: <20221208062955.2546-3-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208062955.2546-1-xiangsheng.hou@mediatek.com> References: <20221208062955.2546-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add optional nfi_hclk which is needed for MT7986. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 719fc6f53ab1..85644308df23 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -297,6 +297,7 @@ struct mtk_snand { struct device *dev; struct clk *nfi_clk; struct clk *pad_clk; + struct clk *nfi_hclk; void __iomem *nfi_base; int irq; struct completion op_done; @@ -1339,7 +1340,16 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) dev_err(ms->dev, "unable to enable pad clk\n"); goto err1; } + ret =3D clk_prepare_enable(ms->nfi_hclk); + if (ret) { + dev_err(ms->dev, "unable to enable nfi hclk\n"); + goto err2; + } + return 0; + +err2: + clk_disable_unprepare(ms->pad_clk); err1: clk_disable_unprepare(ms->nfi_clk); return ret; @@ -1347,6 +1357,7 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) =20 static void mtk_snand_disable_clk(struct mtk_snand *ms) { + clk_disable_unprepare(ms->nfi_hclk); clk_disable_unprepare(ms->pad_clk); clk_disable_unprepare(ms->nfi_clk); } @@ -1401,6 +1412,13 @@ static int mtk_snand_probe(struct platform_device *p= dev) goto release_ecc; } =20 + ms->nfi_hclk =3D devm_clk_get_optional(&pdev->dev, "nfi_hclk"); + if (IS_ERR(ms->nfi_hclk)) { + ret =3D PTR_ERR(ms->nfi_hclk); + dev_err(&pdev->dev, "unable to get nfi_hclk, err =3D %d\n", ret); + goto release_ecc; + } + ret =3D mtk_snand_enable_clk(ms); if (ret) goto release_ecc; --=20 2.25.1