From nobody Sat Sep 21 10:54:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFCF0C4708D for ; Thu, 8 Dec 2022 03:32:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229974AbiLHDcn (ORCPT ); Wed, 7 Dec 2022 22:32:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229795AbiLHDc1 (ORCPT ); Wed, 7 Dec 2022 22:32:27 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFB749854C; Wed, 7 Dec 2022 19:32:22 -0800 (PST) X-UUID: e0aef8f266c540e9b733fac37c9d6aa8-20221208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1VG9jT5xqCzn1Y81lS+7BNjOae3DIvbVuRsqbf3joSs=; b=DZDti5N1ou44/FJQLD5HuZjTEauNCjKgtalJGrLgV57rDvavCONYfSB2EeYJ3uEHymPzmgEof7tjCZhjkOVK2SO6srTmONS4cNd6LvIflWvMxeMN1L60jZm48j6EC302VPs4cEbDciDHxwmlcL8xA8B1gHgxcfPm2orgy/Kk5R0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:af612854-cfd8-40eb-96ef-1c6ed31a4f9c,IP:0,U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.14,REQID:af612854-cfd8-40eb-96ef-1c6ed31a4f9c,IP:0,URL :25,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:dcaaed0,CLOUDID:7318e016-b863-49f8-8228-cbdfeedd1fa4,B ulkID:221208113218CBYB5TLY,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: e0aef8f266c540e9b733fac37c9d6aa8-20221208 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 163598170; Thu, 08 Dec 2022 11:32:16 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 8 Dec 2022 11:32:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 8 Dec 2022 11:32:14 +0800 From: Trevor Wu To: , , , , , , , CC: , , , , , , , Subject: [PATCH v3 10/12] dt-bindings: mediatek: mt8188: add audio afe document Date: Thu, 8 Dec 2022 11:31:46 +0800 Message-ID: <20221208033148.21866-11-trevor.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221208033148.21866-1-trevor.wu@mediatek.com> References: <20221208033148.21866-1-trevor.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mt8188 audio afe document. Signed-off-by: Trevor Wu --- .../devicetree/bindings/sound/mt8188-afe.yaml | 196 ++++++++++++++++++ 1 file changed, 196 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt8188-afe.yaml diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe.yaml b/Docu= mentation/devicetree/bindings/sound/mt8188-afe.yaml new file mode 100644 index 000000000000..6ab26494d924 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8188-afe.yaml @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mt8188-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AFE PCM controller for mt8188 + +maintainers: + - Trevor Wu + +properties: + compatible: + const: mediatek,mt8188-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + mediatek,topckgen: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the mediatek topckgen controller + + power-domains: + maxItems: 1 + + clocks: + items: + - description: 26M clock + - description: audio pll1 clock + - description: audio pll2 clock + - description: clock divider for i2si1_mck + - description: clock divider for i2si2_mck + - description: clock divider for i2so1_mck + - description: clock divider for i2so2_mck + - description: clock divider for dptx_mck + - description: a1sys hoping clock + - description: audio intbus clock + - description: audio hires clock + - description: audio local bus clock + - description: mux for dptx_mck + - description: mux for i2so1_mck + - description: mux for i2so2_mck + - description: mux for i2si1_mck + - description: mux for i2si2_mck + - description: audio 26m clock + + clock-names: + items: + - const: clk26m + - const: apll1_ck + - const: apll2_ck + - const: apll12_div0 + - const: apll12_div1 + - const: apll12_div2 + - const: apll12_div3 + - const: apll12_div9 + - const: a1sys_hp_sel + - const: aud_intbus_sel + - const: audio_h_sel + - const: audio_local_bus_sel + - const: dptx_m_sel + - const: i2so1_m_sel + - const: i2so2_m_sel + - const: i2si1_m_sel + - const: i2si2_m_sel + - const: adsp_audio_26m + +patternProperties: + "^mediatek,etdm-in[1-2]-chn-disabled$": + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 16 + description: + By default, all data received from ETDM pins will be outputed to + memory. etdm in supports disable_out in direct mode(w/o interconn). + User can specify the channel ID which they hope dropping and then + the specified channel won't be seen on memory. + uniqueItems: true + items: + minimum: 0 + maximum: 15 + + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$": + description: Specify etdm in mclk output rate for always on case. + + "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$": + description: Specify etdm out mclk output rate for always on case. + + "^mediatek,etdm-in[1-2]-multi-pin-mode$": + type: boolean + description: if present, the etdm data mode is I2S. + + "^mediatek,etdm-out[1-3]-multi-pin-mode$": + type: boolean + description: if present, the etdm data mode is I2S. + + "^mediatek,etdm-in[1-2]-cowork-source$": + $ref: /schemas/types.yaml#/definitions/uint32 + description: + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm in moudule. + enum: + - 0 # etdm1_in + - 1 # etdm2_in + - 2 # etdm1_out + - 3 # etdm2_out + + "^mediatek,etdm-out[1-2]-cowork-source$": + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm out moudule. + enum: + - 0 # etdm1_in + - 1 # etdm2_in + - 2 # etdm1_out + - 3 # etdm2_out + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + - mediatek,topckgen + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + afe: afe@10b10000 { + compatible =3D "mediatek,mt8188-afe"; + reg =3D <0x10b10000 0x10000>; + interrupts =3D ; + resets =3D <&watchdog 14>; + reset-names =3D "audiosys"; + mediatek,topckgen =3D <&topckgen>; + power-domains =3D <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO + mediatek,etdm-in2-cowork-source =3D <2>; + mediatek,etdm-out2-cowork-source =3D <0>; + mediatek,etdm-in1-multi-pin-mode; + mediatek,etdm-in1-chn-disabled =3D /bits/ 8 <0x0 0x2>; + clocks =3D <&clk26m>, + <&topckgen 72>, //CLK_TOP_APLL1 + <&topckgen 73>, //CLK_TOP_APLL2 + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0 + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1 + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2 + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3 + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9 + <&topckgen 83>, //CLK_TOP_A1SYS_HP + <&topckgen 31>, //CLK_TOP_AUD_INTBUS + <&topckgen 32>, //CLK_TOP_AUDIO_H + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS + <&topckgen 81>, //CLK_TOP_DPTX + <&topckgen 77>, //CLK_TOP_I2SO1 + <&topckgen 78>, //CLK_TOP_I2SO2 + <&topckgen 79>, //CLK_TOP_I2SI1 + <&topckgen 80>, //CLK_TOP_I2SI2 + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M + clock-names =3D "clk26m", + "apll1_ck", + "apll2_ck", + "apll12_div0", + "apll12_div1", + "apll12_div2", + "apll12_div3", + "apll12_div9", + "a1sys_hp_sel", + "aud_intbus_sel", + "audio_h_sel", + "audio_local_bus_sel", + "dptx_m_sel", + "i2so1_m_sel", + "i2so2_m_sel", + "i2si1_m_sel", + "i2si2_m_sel", + "adsp_audio_26m"; + }; + +... --=20 2.18.0