From nobody Mon Apr 13 10:06:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37BCFC352A1 for ; Wed, 7 Dec 2022 14:07:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230037AbiLGOHR (ORCPT ); Wed, 7 Dec 2022 09:07:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230311AbiLGOGh (ORCPT ); Wed, 7 Dec 2022 09:06:37 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D627AA1AF for ; Wed, 7 Dec 2022 06:06:30 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 6D64FB81DE0 for ; Wed, 7 Dec 2022 14:06:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C569FC43153; Wed, 7 Dec 2022 14:06:25 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen , Yingkun Meng Subject: [PATCH] irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4 Date: Wed, 7 Dec 2022 22:06:43 +0800 Message-Id: <20221207140643.1600743-1-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If int_edge/int_pol registers are configured to not be the default values, = we should save/restore them during S3/S4. Signed-off-by: Yingkun Meng Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-liointc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index c116f70929ae..4367ce9b558f 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -55,6 +55,8 @@ struct liointc_priv { struct liointc_handler_data handler[LIOINTC_NUM_PARENT]; void __iomem *core_isr[LIOINTC_NUM_CORES]; u8 map_cache[LIOINTC_CHIP_IRQ]; + u32 int_pol; + u32 int_edge; bool has_lpc_irq_errata; }; =20 @@ -138,6 +140,14 @@ static int liointc_set_type(struct irq_data *data, uns= igned int type) return 0; } =20 +static void liointc_suspend(struct irq_chip_generic *gc) +{ + struct liointc_priv *priv =3D gc->private; + + priv->int_pol =3D readl(gc->reg_base + LIOINTC_REG_INTC_POL); + priv->int_edge =3D readl(gc->reg_base + LIOINTC_REG_INTC_EDGE); +} + static void liointc_resume(struct irq_chip_generic *gc) { struct liointc_priv *priv =3D gc->private; @@ -150,6 +160,8 @@ static void liointc_resume(struct irq_chip_generic *gc) /* Restore map cache */ for (i =3D 0; i < LIOINTC_CHIP_IRQ; i++) writeb(priv->map_cache[i], gc->reg_base + i); + writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL); + writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE); /* Restore mask cache */ writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); irq_gc_unlock_irqrestore(gc, flags); @@ -261,6 +273,7 @@ static int liointc_init(phys_addr_t addr, unsigned long= size, int revision, gc->private =3D priv; gc->reg_base =3D base; gc->domain =3D domain; + gc->suspend =3D liointc_suspend; gc->resume =3D liointc_resume; =20 ct =3D gc->chip_types; --=20 2.31.1