From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2A04C63705 for ; Wed, 7 Dec 2022 14:00:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbiLGOAN (ORCPT ); Wed, 7 Dec 2022 09:00:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbiLGN7n (ORCPT ); Wed, 7 Dec 2022 08:59:43 -0500 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 640045C746 for ; Wed, 7 Dec 2022 05:59:42 -0800 (PST) Received: by mail-pf1-x434.google.com with SMTP id x66so17520744pfx.3 for ; Wed, 07 Dec 2022 05:59:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nbt/wWAyXr8PXcpioECD5vFFYMiQG8G3AvxtqAGhEMs=; b=kFfZArHTfDZyg80wIAXF2jXhRpajwGRdSNrIM3HfbngbOS0QtYcZPhbpe5uywZzdZH eLlbtPhDElNZb29dTOLVwJNEzDn30mD3CXEIsZC1EqXA7i4TtJEXPnRNU9X8C3UG0fKo KcSbcpLX7VnuZANz8Rgq16oceq0ru5Utg4qYw4uQ3nYv3iefE53We/AJ4t+7fHjE5BE2 PGUVRG8oikyKil9hkWrvppK+FobpOF6g9wGO0xzvgulFp4SpAZ8v+N1EuhVcS+YPNfkX YE3gQ5SGN1O8QrWsZkLUlL2+on8lIO3jvDSHWU2o9l6gqXAFf5z1edVF5e4BwwNyiGlD vgpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nbt/wWAyXr8PXcpioECD5vFFYMiQG8G3AvxtqAGhEMs=; b=VgqkB5e/aTp2N6PVib5My3Ad+0QDhU8UJd6LvUOePephO5vBCSIRikLRJy+xAKAS9d 4wbOqoReiYIhI7bScFafPKEvN5Z1hnmfPh3UuNaegvsWQlC2vyPVBxIzzD+IUH5nOgo5 ahvEX2TRX2kHbx1QWu0ftn2NfcUd50BprgsySUKAx+S533GmFnjFg+EJzMFwyNLFMgxs zdf/3uAoHZVOAV+AsolGRUzv2PB+i5kVecdNrG8ZiLQrLfOM3g2NJnpff3EO2EhPaQf2 Qm57crv/nL3r1tKenDzqn9qE/N6w20qHDIl7Ci9YTbq7eGjHeaY7R9YT/vh9CwFJJsvx Ie5Q== X-Gm-Message-State: ANoB5plnpI/2RrSHI5fNSQKTSIly3wGaGRXXTFw8CrjTOzBCDKRFdhS9 PupdmJjBehJQb66SRXFkttcp X-Google-Smtp-Source: AA0mqf4QQLyq9qg7F06RacynLG0Ato69wyZRZbPYGStTm+etW2JDllqAdNf2n23oFnUs7Rv+XpRwpg== X-Received: by 2002:a05:6a00:2883:b0:572:7b49:4f47 with SMTP id ch3-20020a056a00288300b005727b494f47mr76693326pfb.16.1670421581852; Wed, 07 Dec 2022 05:59:41 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.05.59.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 05:59:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 01/12] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Wed, 7 Dec 2022 19:29:10 +0530 Message-Id: <20221207135922.314827-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Signed-off-by: Manivannan Sadhasivam Acked-by: Sai Prakash Ranjan --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller =20 maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan =20 description: | LLCC (Last Level Cache Controller) provides last level of cache memory i= n SoC, --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C1BEC63706 for ; Wed, 7 Dec 2022 14:00:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230264AbiLGOAU (ORCPT ); Wed, 7 Dec 2022 09:00:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230220AbiLGN7t (ORCPT ); Wed, 7 Dec 2022 08:59:49 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7733E5C75D for ; Wed, 7 Dec 2022 05:59:48 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id k88-20020a17090a4ce100b00219d0b857bcso1714708pjh.1 for ; Wed, 07 Dec 2022 05:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vwHmJ0i8eRrdJL4Dl+R0aoA35/USIsHe1f5AGZFuBf8=; b=OD+cAweOssXB7azBKYQhL+0oMitp8X6VJm/J895F1RNtF5D7DB1DvZ5FPUk7WhE8rw isXLpinkr3G7y9cKcfV3FnVjIDieOZatDAOcVxyNQ/vwXiL23F/naOEvoVsgsgG9P8mJ GpDJEYXA4NF6NoPM0+ueSkwmAgMnHOX//uHCAHEg/YNYNOAFmpsEwygOVZ5ovSLVKArw i9yqbZ9pGodF0R+JWSoyxYQB+cwRwNq9HHY0ejgPlBCDZB+ZAXwn0lD1Ajq33IPwBAm6 pHeHa4+QnZ1kMCk533DbWJILyP2X2/MlBW3bFWfjJ4tjwc9fTYTN65ZEChSzaHG8udnU cZzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vwHmJ0i8eRrdJL4Dl+R0aoA35/USIsHe1f5AGZFuBf8=; b=vxIs7xZXmwyyM/hDB7Dy7u2w6JhF5oJnxCNrhi33XM0KsMk/ZaLrSEXar76wDYaDtY akuBKNXlsvdRdmBcOH+1yZsp39B6BGUTjsEqcVWRpbTlpn7ac624Ch0V/fwwvfGP2ooe rqo9q4KoaeK4ODg7lEGinHod5QHD8ka+CSBSLP4S3gSxUmh7HqZ0u3MpA5TTpBVsrL1L dU0Wim606kNo9UtegmSmF9UWTMzyYm60S9fNP88l4fLjBe4VNJ978hiRpoK4bw1MM5fQ PYhcj3AlpgRbSLGsYgOzhzgm90Ky4/5Gc0iJq10acH59FZ43ybeqCwhD6PAz/ffNRKdb 6OAA== X-Gm-Message-State: ANoB5pnK81FgkywrFMpLqmKg51h9wBPG4Idr83jX6/e5ZnIdyGGJpppK msRSBjp7mXwlJPbqsuQlXKUa X-Google-Smtp-Source: AA0mqf6NdZEB+vu0KzJADmdPGIY1PLQc10iKrjmXLFRFsLnXOzvyvN7SngE59U2WWlLhLkXXNN7N3A== X-Received: by 2002:a17:902:e005:b0:189:c62e:ac2f with SMTP id o5-20020a170902e00500b00189c62eac2fmr21071383plo.144.1670421587941; Wed, 07 Dec 2022 05:59:47 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.05.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 05:59:47 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 02/12] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Wed, 7 Dec 2022 19:29:11 +0530 Message-Id: <20221207135922.314827-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Register regions of the LLCC banks are located at separate addresses. Currently, the binding just lists the LLCC0 base address and specifies the size to cover all banks. This is not the correct approach since, there are holes and other registers located in between. So let's specify the base address of each LLCC bank. It should be noted that the bank count differs for each SoC, so that also needs to be taken into account in the binding. Cc: # 4.19 Fixes: 7e5700ae64f6 ("dt-bindings: Documentation for qcom, llcc") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..7f694baa017c 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc =20 reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 =20 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 =20 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false =20 examples: - | #include =20 - system-cache-controller@1100000 { - compatible =3D "qcom,sdm845-llcc"; - reg =3D <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names =3D "llcc_base", "llcc_broadcast_base"; - interrupts =3D ; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + system-cache-controller@1100000 { + compatible =3D "qcom,sdm845-llcc"; + reg =3D <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts =3D ; + }; }; --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E11EDC4708E for ; Wed, 7 Dec 2022 14:00:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbiLGOAe (ORCPT ); Wed, 7 Dec 2022 09:00:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230036AbiLGOAB (ORCPT ); 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Wed, 07 Dec 2022 05:59:53 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 03/12] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:12 +0530 Message-Id: <20221207135922.314827-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.4 Fixes: ba0411ddd133 ("arm64: dts: sdm845: Add device node for Last level ca= che controller") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 65032b94b46d..e1c0d9faf46e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,11 @@ uart15: serial@a9c000 { =20 llcc: system-cache-controller@1100000 { compatible =3D "qcom,sdm845-llcc"; - reg =3D <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C94C4708E for ; Wed, 7 Dec 2022 14:00:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229586AbiLGOAk (ORCPT ); Wed, 7 Dec 2022 09:00:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230253AbiLGOAE (ORCPT ); Wed, 7 Dec 2022 09:00:04 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2B82D2F6 for ; Wed, 7 Dec 2022 06:00:00 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id b13-20020a17090a5a0d00b0021906102d05so1706153pjd.5 for ; Wed, 07 Dec 2022 06:00:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iUBfene/cnQwgTF0aG4S0NjKk1KSg5LGCh8ripuPt50=; b=H8wT7XpkqvaHjQ6Po/goMKj6V6jL/8Ey8Hf+GqZvdwrHx75UStaopLvvwyARJc7qO5 5UoJNpiMgUPfBpM1ZyE6UT7VLrFXYXeoGRckbpFv5xvbBUxLlTvOj8sqS5KRCwaQ1Fzi qztmo5Z4rB7+/QyLfJCSJIa1uG7AvVCX3XtsZI2rC5nfb6nvLpRJVPky+FSR204kiFNF BhDV1+OswALIVZavXenT6tiQ01rKxTbsg/oMCnlYCKLWTf2TB5yWAC2oFsw/AWa0/HNF z0gAf7S5LzBhpitYnxVtjOdLT50vK76PfjLoQfcJFur8TtrtNyauTbmHDx3nnT3sDQXT x+vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iUBfene/cnQwgTF0aG4S0NjKk1KSg5LGCh8ripuPt50=; b=Ts0RKXJ+vKb6CquR3ffR8VbqTeDWWyS07Bg9Z/Dte5tKaLIg1mj/c3eWmK7mcYttGI U7lyFZLVqcPFVywinYV9EkLbhRy+jZ3tjFvEc286GP6HMPVWQMfR9F5nEKoPlSOzkUSm Drr8CmAIC23mrWWqTrMOICHDEvk1UF7nCs/mwnOd6KNk5pfdSuYowoEy3vWDFdppEpmy 99X1DBPBDEbrgiVkpG3UffNX1skzAyGAraoSivhV+7xEx55wxOR0XohVq8J15SWYHGuT H2hsZn0+AI6ohsS657+7uXrDBOmnB/8A7ckWprUcSye4f7PCEsdbLILCxTLWNlsjG8EU adPw== X-Gm-Message-State: ANoB5pna73VhWz5vbS9Oy9oNQLDJJXrYFEdzoZaZqSAbd+2DyxLB2Yde MsTC2hd3PLHDTPnosMfE1ctJ X-Google-Smtp-Source: AA0mqf6BwCJ/ScoZvW+2XcQjX3QSYrL5niNqC+Kve9LZHguQz+jHID3tQYcmqCpRfB+QgrDtXk0OYg== X-Received: by 2002:a17:90a:3da1:b0:219:61e5:4994 with SMTP id i30-20020a17090a3da100b0021961e54994mr37329693pjc.213.1670421600398; Wed, 07 Dec 2022 06:00:00 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.05.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 05:59:59 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 04/12] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:13 +0530 Message-Id: <20221207135922.314827-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Cc: # 5.6 Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache contro= ller node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index f71cf21a8dd8..f861f692c9b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sc7180-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg-names =3D "llcc0_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00A59C4708E for ; Wed, 7 Dec 2022 14:00:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230144AbiLGOAr (ORCPT ); Wed, 7 Dec 2022 09:00:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230255AbiLGOAM (ORCPT ); Wed, 7 Dec 2022 09:00:12 -0500 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 475575C0F9 for ; Wed, 7 Dec 2022 06:00:07 -0800 (PST) Received: by mail-pg1-x52c.google.com with SMTP id 6so16445199pgm.6 for ; Wed, 07 Dec 2022 06:00:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5n0Bzk4oRcwoQ/X+7mKiinSvd0WlsPB4Sg7t77MHfrg=; b=bDfohewvK322PkyoaoeVx5utUGw02oRSdwD7E5T8JwmGQGI+eGv/eQmEAHEeI4vGL5 hZP4IorHbJ7MPDJkhHCOylqWDMSvmVSbLnJFLDTIEgY332WwAzDu189nbcYWtp+S4rNi z9STzDjpH/T0zBBOuHixzfS0FAqQNeMFZQf32hyw3yJhIIa909ZYhOuXKdNHbdafKcCl x4pcKDcJrV4bKkKB5rVESJiPcJMHfFC9n+KwxTy5Um5J2DkyeLigZnE0kjnzUawwxsDi JpmdU2q2fGPdoQvAiatfiJlIBZ+xxYPaPQ/CgfmUda81/rErjmpxirMtZgJtL6fg1qta Tq1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5n0Bzk4oRcwoQ/X+7mKiinSvd0WlsPB4Sg7t77MHfrg=; b=WtXlqZjlG0t44CEqnKB9qIEl+UObVPBg93+OMv++n5YuZSD9Gw+3ILsxnAHTyBWSN7 QHymjqwrtrSEdZEmyLepmDbJn/OjMkAcJKQ4XsAip88EDCcZNVZ9TsdkWI2oSe0GngYI ifhJeIm+pgapUk14kL7H4Nu7abH646e3LKS2Pe9KB4I2OQFYSujFUFJjYnrFbg0NbPF0 Ge51j3UhAQwzkvnp72qeXfKX7y/tUvjtZOjbUeLP0UmsMamfzn6HtYNQ0doHIC8xC/Yx jD7SGYMC/7CBuYdIK9cEdFRrCcxqD1oGuU+FPVP4EXrOx0cco8k3ArPjanRfdrJZKnUl SF2Q== X-Gm-Message-State: ANoB5pmW9jI4uSMKNr3d2VxaYrlzFXGC3njRWfp1g/KKtMwLvlA3nJbA hyBGAQlseHvJjPU2rYDy94W5 X-Google-Smtp-Source: AA0mqf7B1Q/KziWYaacazkXY2TuYKm/263tGdPPAdJ/GFN2M21J5u/BfEWI8V+2vKrdEBpBV0oyxOQ== X-Received: by 2002:a63:5b4d:0:b0:478:ae0a:bd86 with SMTP id l13-20020a635b4d000000b00478ae0abd86mr15223904pgm.239.1670421606382; Wed, 07 Dec 2022 06:00:06 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:05 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 05/12] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:14 +0530 Message-Id: <20221207135922.314827-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Cc: # 5.13 Fixes: 0392968dbe09 ("arm64: dts: qcom: sc7280: Add device tree node for LL= CC") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 0adf13399e64..6c6eb6f4f650 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,9 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc7280-llcc"; - reg =3D <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED8A8C352A1 for ; Wed, 7 Dec 2022 14:00:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229667AbiLGOAx (ORCPT ); Wed, 7 Dec 2022 09:00:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229678AbiLGOAU (ORCPT ); Wed, 7 Dec 2022 09:00:20 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C713A6415 for ; Wed, 7 Dec 2022 06:00:13 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id w15-20020a17090a380f00b0021873113cb4so1736037pjb.0 for ; Wed, 07 Dec 2022 06:00:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jGefmKMEXqWoGu7xIFjnC5m/g9TolIorwDYvhcWeeRg=; b=oJK7a30Mr2LkFqooyVg0pm63JlyQOjxUpyH9huMRz1fbq5VA3YR5KjoaoRdBcl+i88 A7DAAvJDi78hXvVmHf1AWOrZ7jAOnfomvc+ch7/fUd8RHbzmSkrxt7KeTpXaTV9VJ0a+ lnwhKxRY01WNGsIrusLM2xijeXHZvrMbO2fRUeWZCMTc1ewPPzxadUdtIZO81hQ5swr0 21QVZveUsYIfw3yrvmKZVec0rRAu1/18evngrlhb2Er0TOq8Yb82F726ctjooUwYIcVx c5LI0N+WmGnJd5swAWQbcaG/MY3QZSTyQT8gw9ezKxkVckL5+bT5hcbm73WTozlUGRnN ASTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jGefmKMEXqWoGu7xIFjnC5m/g9TolIorwDYvhcWeeRg=; b=Fvvm52vY1olnDsmudFgR1dkp/bingUiqqYUObHbaG/goYVN0PsHPhuACbFYwXOtOq8 fDcya0x0BnQw5dmlcIhq7ExwKSj1/6Dszqhf1s6BARzoYJzoFDbWT49vTTAW91WhWhZJ j/84j8qpf//t8n8klHVhAcfDwDWPgA3j0c4Gmb8BsWJpAltF5pgYSnW8L7Ny3g67vwdk X28qeHB8J10kLDudM8V1duoPT3mVQYtxSHSQ2pSAEiWzMuk+W3va6zw0561ULulUfcZG eING3PquV4+bJB+o+rROHT+F8D7Gdq6PsdzRIyDRoZleT+PDMp7B/ihOYIUIxSNNeQfO QCLg== X-Gm-Message-State: ANoB5pl6p3W6IVbcfgH0QXCPvoijZhnu8fdbpkBrYGp+keU0R53m6z8/ gdpGf+ElPgEIDOZTcyBGXvCT X-Google-Smtp-Source: AA0mqf4zcdu1I6R57Zdsr7a6QFCdrc4ms6nXqRhPXfMXqpJqJsAtmwTd57t6p5rBlswXOWu2573K6w== X-Received: by 2002:a17:903:181:b0:189:8f11:f2f with SMTP id z1-20020a170903018100b001898f110f2fmr48579907plg.133.1670421612815; Wed, 07 Dec 2022 06:00:12 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 06/12] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:15 +0530 Message-Id: <20221207135922.314827-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 6.0 Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 109c9d2b684d..0510a5d510e7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,14 @@ opp-6 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc8280xp-llcc"; - reg =3D <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD9ADC352A1 for ; Wed, 7 Dec 2022 14:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230258AbiLGOBB (ORCPT ); Wed, 7 Dec 2022 09:01:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230220AbiLGOAW (ORCPT ); Wed, 7 Dec 2022 09:00:22 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E9DF5C757 for ; Wed, 7 Dec 2022 06:00:20 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id jn7so17086703plb.13 for ; Wed, 07 Dec 2022 06:00:20 -0800 (PST) DKIM-Signature: v=1; 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Wed, 07 Dec 2022 06:00:19 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:18 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 07/12] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:16 +0530 Message-Id: <20221207135922.314827-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.11 Fixes: bb1f7cf68a2d ("arm64: dts: qcom: sm8150: Add LLC support for sm8150") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index a0c57fb798d3..7fd2291b2638 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,11 @@ mmss_noc: interconnect@1740000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8150-llcc"; - reg =3D <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A20CC63705 for ; Wed, 7 Dec 2022 14:01:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230294AbiLGOB3 (ORCPT ); Wed, 7 Dec 2022 09:01:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbiLGOAh (ORCPT ); Wed, 7 Dec 2022 09:00:37 -0500 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C73C85CD2F for ; Wed, 7 Dec 2022 06:00:26 -0800 (PST) Received: by mail-pg1-x52c.google.com with SMTP id h193so16438248pgc.10 for ; Wed, 07 Dec 2022 06:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m9wB8HfZl3VNPDfTiqbYvNGJ+C+gB7rjqwIL9QWVnZY=; b=bGJ7XILZ3JHnO065vPE2FpcT5z5uAqEEOiqARKZHZKX1ckjPjdgSBW7/EndyCXEewr Q49oC/fEuNxkoKmzhr4ydHYcnY/AnyBBqMg6hHvdJx6UNHEnOK6ztT3ZsF10V95wIT2g kHVfZoBPYd6qYAEOulgTgIkd/uCLB8iNs3zR05aOc8sx1Agb+jxQGS1HhfcyNb27QmQ2 NEQ7/ND6zf+R1aE1JkeEx0SBmyDRR2nGxpla/+RU8aJwD2J98sCU0a/gdL/W222S04ZL p4won3uXWRqZ7DrpQdS5Ftrql3RkrA06ZQGB8yP0Tsf5iX2zC7wyjo667mA/AlZydMjc Ui6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m9wB8HfZl3VNPDfTiqbYvNGJ+C+gB7rjqwIL9QWVnZY=; b=bFkU7/behHwxT44COm/DztrQfL0KTQX2P8fDDywwYz08Z4RPI+M8Z8aBT8N2WrUrDH /QpUdnJVKefVmMPG+Y6+qmfdkxxOFrniHXX4C+nsL7TZS1iFhTaAjlEh33wNNV5Hhth6 S4PT60zI98PJZ44pYxX4yogzCZNOM+nz3ykXiMt53j4yZIpGF1baUACVRKb7V+9Tb4/d kL8NkayrITo3RXg3naW4VQvd0jz6dnHw0G1Ien483gb01zGIa/sIhW0nELVaSGLBm3s1 L6Ujn9sFt9YmpTZ6+RWz/7X6+FRhkTKMUS6TOGfxsxI3D/1e/wnu7P7kQRvQH0J8g5PG d4ww== X-Gm-Message-State: ANoB5pmbduU7I+zpZrEC2olcwDpu7VEHAnBxZx8AzXm5ipa8tQZFvbrb oA1kr1KsxFp3hYhi/Pv44GM5 X-Google-Smtp-Source: AA0mqf4JhLpEzJBzUDoRUDShe0fazOM5Kybl/zUECelo4UCHl7ghB2yXwXg+IkCFhIl8itdGB0URaQ== X-Received: by 2002:a05:6a00:1ad2:b0:576:f761:d381 with SMTP id f18-20020a056a001ad200b00576f761d381mr14371016pfv.59.1670421626221; Wed, 07 Dec 2022 06:00:26 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:25 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 08/12] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:17 +0530 Message-Id: <20221207135922.314827-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.12 Fixes: 0085a33a25cc ("arm64: dts: qcom: sm8250: Add support for LLCC block") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index dab5579946f3..d1b65fb3f3f3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,11 @@ usb_1_dwc3: usb@a600000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8250-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; =20 usb_2: usb@a8f8800 { --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA3D7C352A1 for ; Wed, 7 Dec 2022 14:01:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229829AbiLGOBh (ORCPT ); Wed, 7 Dec 2022 09:01:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229918AbiLGOAo (ORCPT ); Wed, 7 Dec 2022 09:00:44 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B32E5CD32 for ; Wed, 7 Dec 2022 06:00:33 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id e7-20020a17090a77c700b00216928a3917so1511297pjs.4 for ; Wed, 07 Dec 2022 06:00:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vfunYPN7pQzIq/aXuuYsh9BqM9fjFphrjnxLDwW5HDM=; b=P/D+hvsSzs5/Z2g+hUwoSTGiCaJQRcrqbPrEN3djw3epYnLFlbXktZajYPahX5bTnY Ro130UAGILR62rxsSXDZ7b5kM6S6yvNxWGoq6LVWl79Cajn0bPQT8OKkjger2zTNuBdS k0FP8H1x1NWDJIX+j2/Biaw23GI/3/Z5n3tGFa6Ukd3rUkE8MuO8K6pin/D18dIXOuxo jc28OHhgT2kWkqoZaoSe0TbvkPulj4hBNI7Vwmuks4Bn5Psj/0oIWEUx/Vf0iCkiKRUP bSDza/ogKT+CSehmv3ULvp/XU5wOSlCTAYvUxvXzUg+IC8mMa88hlA8wg5d2pdRPwa+K nsQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vfunYPN7pQzIq/aXuuYsh9BqM9fjFphrjnxLDwW5HDM=; b=5ROpAk1h2P6eR1pNxFpnuYZrhrpCIIaz8NZD5h7DJwLb4lwY2+To9Zxj8NDoQ3o2mO BlTEK4uViwfHm0wNbqrhk5iD1P/ANrYgWLITFU/j89yESh81LXvx71hvcRiyOkqZz2mE d9klbYc+D7l/rv/P1CiBcNjbM/dMoOXtvFFCEP8YQm8ejXbDMe8HeSqj0WIAvoyrBmXj p/OdKej2KwOMAehuZXPbrmObA5p7O0vPk8VZwX24oOQaElv1Qv6OdGcKKL0nu4Y/u4yZ 3zCnkxUpSW6Bwy5JgwNxrRKHmB0GMyfY/9Ka1Qj15pr8i5229RQUHHPTpqularNVtVBQ UxfA== X-Gm-Message-State: ANoB5pmZunRfmqDi2/l0BtGFfN2bA6dSgjOOjod4rhLx4ZNuw8qZ4iLe KJ1TRun6QKdplbP5QGSj//xo X-Google-Smtp-Source: AA0mqf6e6lJbaOA8uQds3om0jADfzRMHAvMsP7NLMRU5y1QZh9n7PUcvTRC/GPic/srqltROqfBZrA== X-Received: by 2002:a17:902:ed94:b0:189:66dc:4af4 with SMTP id e20-20020a170902ed9400b0018966dc4af4mr59310310plj.149.1670421632460; Wed, 07 Dec 2022 06:00:32 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:31 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 09/12] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:18 +0530 Message-Id: <20221207135922.314827-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.17 Fixes: 9ac8999e8d6c ("arm64: dts: qcom: sm8350: Add LLCC node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 245dce24ec59..836732d16635 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,11 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8350-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; =20 usb_1: usb@a6f8800 { --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41CD7C4708E for ; Wed, 7 Dec 2022 14:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbiLGOCo (ORCPT ); Wed, 7 Dec 2022 09:02:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230058AbiLGOBM (ORCPT ); Wed, 7 Dec 2022 09:01:12 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9349D12745 for ; Wed, 7 Dec 2022 06:00:39 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id 82so16500147pgc.0 for ; Wed, 07 Dec 2022 06:00:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4HXFRaipNAA/3SVXX4rMylP7rXb8WAB5NgKEFsbHAGk=; b=mIbtkx5ZYYnroshvQ2t9MPgSjjE3QsY4ZeLxclpuzT+W76Iwc3E11RHLejCqci1+D9 9WtB0A54+LWedD3UwQkLkB7LEmqvAY19WypkTGi+TXwbf/fjH/kk4nLeRLs7zVaYUvbA t23Qsx47tB0Fi00bZVv6ftKAJpO+PHeY+S218JUg5vGPFUYP0/ZAfmKzO4vuBt+5nohQ kDZLJJN+R/wPCeKIRBKNg3Z4/aCacZsBCsm2lZSKTbEG+tunELjGU+pfhRlSfAvJqoJj MEBna6VUxY/BmXsUnS8lGe8zjELxJoq3DwXBJkJSvs85ARPApD8fxgKplvqbznD442t4 AedQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4HXFRaipNAA/3SVXX4rMylP7rXb8WAB5NgKEFsbHAGk=; b=MCd+LHHPRUgAW9DlBbt/WIBIR0IkqqYLN3syAkWadEe2acnBnNU0qUyqaWdDSrvbau b3Fn5vSGs13Tmf+rg30lJSyFiXzRNGJl2AjNsZXShaB/s6EoVuWE5WvmC9l1SN347xQi l/7WP7Z9AGls3LnqA/CJNn0YRpMfwfAckeIJxEvwJLKeVBEatkxVmgtJl0uOQ+qj/GIl krs6WVm/vnvuBQwvBJuHU9kYGKmUY2iyORbdrGSHdSTx3p9GN5h9p58neaStkyx2XFmv JTgZj9yDRoAaV9gt6YQU29DoVitFe7jALKs4+OCqfUUO/cxOu86GSrgtyRtoBx6QWAzg F8KA== X-Gm-Message-State: ANoB5pnh8CDDEn4Lki9m0V8nFNjlwIjgbmlJQp2FSxR/UmGQC6cVb6jo 3ha1Xc4oiNFHh3RxMyBswiWB X-Google-Smtp-Source: AA0mqf6PkeIpX8wdc7FSgLEftKEzJvmNEAp1iukvNMuqhE5V8GCSkPkULyLzQqbsPZY9MO2mkEQy8w== X-Received: by 2002:a63:eb16:0:b0:477:6fe1:cd6d with SMTP id t22-20020a63eb16000000b004776fe1cd6dmr69810826pgh.334.1670421639019; Wed, 07 Dec 2022 06:00:39 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:38 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 10/12] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:19 +0530 Message-Id: <20221207135922.314827-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.18 Fixes: 1dc3e50eb680 ("arm64: dts: qcom: sm8450: Add LLCC/system-cache-contr= oller node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 570475040d95..12549a2912c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,11 @@ gem_noc: interconnect@19100000 { =20 system-cache-controller@19200000 { compatible =3D "qcom,sm8450-llcc"; - reg =3D <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E38B0C352A1 for ; Wed, 7 Dec 2022 14:02:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230165AbiLGOCg (ORCPT ); Wed, 7 Dec 2022 09:02:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229928AbiLGOB2 (ORCPT ); Wed, 7 Dec 2022 09:01:28 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B89C65D684 for ; Wed, 7 Dec 2022 06:00:45 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id s196so16476448pgs.3 for ; Wed, 07 Dec 2022 06:00:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AGwgSnOhYi02xVu+IbkUS49u1T5vi+3uXVqLwkjF92c=; b=RelowFhh6oDnHAyNKyX5GbA0mViEyG82HTuOCWYZ5qrEcSdJzwUBvwFBBkWMWJVLJS XQ3r67OTKq+d0YJ+zYjUP+DwVXu6cA4OsIXmXxXwuJz0ZYIEj2jbu7bUdy/uIB64TN/B 3wp1Jd1vmyS5dBY19RdVefXiyHrbBtesuuq5FyzuRz0fd3ZAWF+Mbz0rRWgrPWxl2EWt DDesFiVgla6qIu4YzL9mosel0xcmbHZQ4Q913AxLMXeXPl67p9ko9DuQWmDMSrp9yxgt 5kM9BPICjX/IMuGDeziQRWvE5dnp7fZGCifql6pp8otxSixvDtscV77RApqMb76xzJc8 +Kag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AGwgSnOhYi02xVu+IbkUS49u1T5vi+3uXVqLwkjF92c=; b=b9wreoZjph7Q2fpGT4SNSj9ef3S1SAeSR2Ta4RUYceFCEENPiksnY6bcW7XGNPZesL ng1diop/lA/YGaXhz9Av5I7kmMq2mD38Pgh9T1UiXewrbqlvX3AT8bcqDGEcf6/Ks0pi VNUAyOrY4++3hlUba7hiqPVlp8MNz6qqb8K5UuOUL570cPDlzbHODJzNMpYpvqT2wHFA m97TiAjHfhTP2EAstJ1U0uH7nJ9IE77mLdfLtYZI9xxW0r8Akt0uteseGQkggN45TLB0 fgZbeP+4VUmf5OoIwmHoNoWLJz+dLd2Sz56BvOJcbWA10xPem+9aJ/cHHvWMGWHIvT9P SLGA== X-Gm-Message-State: ANoB5pkZKzKBq+Kqu1XQm5QobKa+6rcT3zD6Xo1BEb3JgGtVKhyPxox/ DvaCFt/DaKaeEzw/TeiI8rhF X-Google-Smtp-Source: AA0mqf4xthVb9iLjHkSf+QcyPhznIdyUnH2woOTMyd/m/Su3Q10nTYhwPFoFW3QGv3znCqBN5a1TjQ== X-Received: by 2002:a62:ee0f:0:b0:56c:8dbc:f83e with SMTP id e15-20020a62ee0f000000b0056c8dbcf83emr73052440pfi.41.1670421645105; Wed, 07 Dec 2022 06:00:45 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:44 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 11/12] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:20 +0530 Message-Id: <20221207135922.314827-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Cc: # 5.16 Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 43324bf291c3..c7701f5e4af6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sm6350-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg-names =3D "llcc0_base", "llcc_broadcast_base"; }; =20 gem_noc: interconnect@9680000 { --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85450C6370E for ; Wed, 7 Dec 2022 14:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229437AbiLGOCc (ORCPT ); Wed, 7 Dec 2022 09:02:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230312AbiLGOCB (ORCPT ); Wed, 7 Dec 2022 09:02:01 -0500 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2F8C5E3EF for ; Wed, 7 Dec 2022 06:00:58 -0800 (PST) Received: by mail-pf1-x42d.google.com with SMTP id n3so13247053pfq.10 for ; Wed, 07 Dec 2022 06:00:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NhWX6rKQWUP57iw8+d4GFT7tQjEcrRRRTsFAecr4akA=; b=A9v9lLV56An3GhPsH89Ik473JrofRyBdoLoOAQPzQLQbyppH1iHysZpC0Uli4f28PT Jr+UzCAhJ4Wmoy3JXe25IScBIloO1gSmuRDg/+uUUiSrFA3Ynl/fFocpgyVhDgy4zcOM qjjxN2afRdMvUNXqPEmQQ+764HOjVcqIxAHRYgPi+ape3usBOAhruzcg2KTwLGMDc/wO yqYuQBDDfPOooe0BZ/f8ZXZQPlGYCAovECjM7P7/RSySESbiVolMeg4tljpXO7yboMlE VkUz0E2umgbcDz7IPJcOYaAsUgoxzeJ6NNR8J1XfkRA8WO8KFS6R38WBc7ozgXuvZQMF uZfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NhWX6rKQWUP57iw8+d4GFT7tQjEcrRRRTsFAecr4akA=; b=qntn7KzC6vAJH7p0PNaNPHxZs3BxbCbuvTSQwvOeqzByT9HPIr1Dfa8HtETepUMjJo gpCglwQycPYt4lER8DXWeMiFCSlDnXPvIJxrlhHEu8RhDZSGoBr2H+hJ2ovqaIYmzcS3 JKmRxQ3gYrjU4V84erBG2pN7+VkLVAILkQ5Zfo/ISbtSBR8542pjd5JRXWWsKKH/h+NV FJLkp+OwOPn6LpPh4LZ8Ao/6URwo94zdCbx8uVLTthUdJ2u2ugNuuQvWUhWyn/YO98Sg S0Z5HeLht+6sQ8g9bMwx2nRFtbXknhb3iG4HRlo/WaJmLaduqatwgBtTkNFsspJT6phX XpXQ== X-Gm-Message-State: ANoB5plrJ6IH96kE7uzHszLpAq74tKfU3scVqsL0pLOhjGTiF/H/4T41 uH5PDV0HAFlRb5kavdMl2gVY X-Google-Smtp-Source: AA0mqf4RYtHL2QYHXNhUfXa/ongclBqtFtdfIORIDRXHajHgTCyU9tFwKK+wtOPwDBZD/b7xdrRcJA== X-Received: by 2002:a65:5aca:0:b0:478:b2d5:d843 with SMTP id d10-20020a655aca000000b00478b2d5d843mr14474926pgt.415.1670421658483; Wed, 07 Dec 2022 06:00:58 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:57 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 12/12] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Wed, 7 Dec 2022 19:29:22 +0530 Message-Id: <20221207135922.314827-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. Cc: # 4.20 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++---- drivers/soc/qcom/llcc-qcom.c | 64 ++++++++++++++++++------------ include/linux/soc/qcom/llcc-qcom.h | 4 +- 3 files changed, 44 insertions(+), 38 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..70bd39a91b89 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) =20 for (i =3D 0; i < reg_data.reg_cnt; i++) { synd_reg =3D reg_data.synd_reg + (i * 4); - ret =3D regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret =3D regmap_read(drv->regmap[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, i, synd_val); } =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret =3D regmap_read(drv->regmap[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret =3D regmap_read(drv->regmap[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) =20 /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret =3D regmap_read(drv->regmap[i], DRP_INTERRUPT_STATUS, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc =3D IRQ_HANDLED; =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret =3D regmap_read(drv->regmap[i], TRP_INTERRUPT_0_STATUS, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..7264ac9993e0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 =20 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; =20 drv_data =3D devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,12 +933,46 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) goto err; } =20 - drv_data->regmap =3D qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret =3D PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap =3D qcom_llcc_init_mmio(pdev, "llcc0_base"); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); + goto err; + } + + cfg =3D of_device_get_match_data(&pdev->dev); + + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], + &num_banks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + drv_data->num_banks =3D num_banks; + + drv_data->regmap =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regma= p), GFP_KERNEL); + if (!drv_data->regmap) { + ret =3D -ENOMEM; goto err; } =20 + drv_data->regmap[0] =3D regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i =3D 1; i < num_banks; i++) { + char *base =3D kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmap[i] =3D qcom_llcc_init_mmio(pdev, base); + if (IS_ERR(drv_data->regmap[i])) { + ret =3D PTR_ERR(drv_data->regmap[i]); + kfree(base); + goto err; + } + + kfree(base); + } + drv_data->bcast_regmap =3D qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { @@ -947,8 +980,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } =20 - cfg =3D of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret =3D regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_H= W_INFO], &version); @@ -957,15 +988,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) =20 drv_data->version =3D version; =20 - ret =3D regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0= ], - &num_banks); - if (ret) - goto err; - - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; - drv_data->num_banks =3D num_banks; - llcc_cfg =3D cfg->sct_data; sz =3D cfg->size; =20 @@ -973,16 +995,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices =3D llcc_cfg[i].slice_id; =20 - drv_data->offsets =3D devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret =3D -ENOMEM; - goto err; - } - - for (i =3D 0; i < num_banks; i++) - drv_data->offsets[i] =3D i * BANK_OFFSET_STRIDE; - drv_data->bitmap =3D devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index ad1fd718169d..4b8bf585f9ba 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmap; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; --=20 2.25.1 From nobody Thu Sep 18 10:01:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC01EC352A1 for ; Wed, 7 Dec 2022 14:02:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230265AbiLGOCw (ORCPT ); Wed, 7 Dec 2022 09:02:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230101AbiLGOBz (ORCPT ); Wed, 7 Dec 2022 09:01:55 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09F535E3CF for ; Wed, 7 Dec 2022 06:00:53 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id o12so17663335pjo.4 for ; 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Wed, 07 Dec 2022 06:00:52 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:51 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 12/12] llcc/edac: Fix the base address used for accessing LLCC banks Date: Wed, 7 Dec 2022 19:29:21 +0530 Message-Id: <20221207135922.314827-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC driver has been using a fixed register offset stride for accessing the CSRs of each LLCC bank. This offset only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. Hence, obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. Cc: # 4.20 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++---- drivers/soc/qcom/llcc-qcom.c | 64 ++++++++++++++++++------------ include/linux/soc/qcom/llcc-qcom.h | 4 +- 3 files changed, 44 insertions(+), 38 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..70bd39a91b89 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) =20 for (i =3D 0; i < reg_data.reg_cnt; i++) { synd_reg =3D reg_data.synd_reg + (i * 4); - ret =3D regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret =3D regmap_read(drv->regmap[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, i, synd_val); } =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret =3D regmap_read(drv->regmap[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret =3D regmap_read(drv->regmap[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) =20 /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret =3D regmap_read(drv->regmap[i], DRP_INTERRUPT_STATUS, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc =3D IRQ_HANDLED; =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret =3D regmap_read(drv->regmap[i], TRP_INTERRUPT_0_STATUS, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..7264ac9993e0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 =20 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; =20 drv_data =3D devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,12 +933,46 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) goto err; } =20 - drv_data->regmap =3D qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret =3D PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap =3D qcom_llcc_init_mmio(pdev, "llcc0_base"); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); + goto err; + } + + cfg =3D of_device_get_match_data(&pdev->dev); + + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], + &num_banks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + drv_data->num_banks =3D num_banks; + + drv_data->regmap =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regma= p), GFP_KERNEL); + if (!drv_data->regmap) { + ret =3D -ENOMEM; goto err; } =20 + drv_data->regmap[0] =3D regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i =3D 1; i < num_banks; i++) { + char *base =3D kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmap[i] =3D qcom_llcc_init_mmio(pdev, base); + if (IS_ERR(drv_data->regmap[i])) { + ret =3D PTR_ERR(drv_data->regmap[i]); + kfree(base); + goto err; + } + + kfree(base); + } + drv_data->bcast_regmap =3D qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { @@ -947,8 +980,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } =20 - cfg =3D of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret =3D regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_H= W_INFO], &version); @@ -957,15 +988,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) =20 drv_data->version =3D version; =20 - ret =3D regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0= ], - &num_banks); - if (ret) - goto err; - - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; - drv_data->num_banks =3D num_banks; - llcc_cfg =3D cfg->sct_data; sz =3D cfg->size; =20 @@ -973,16 +995,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices =3D llcc_cfg[i].slice_id; =20 - drv_data->offsets =3D devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret =3D -ENOMEM; - goto err; - } - - for (i =3D 0; i < num_banks; i++) - drv_data->offsets[i] =3D i * BANK_OFFSET_STRIDE; - drv_data->bitmap =3D devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index ad1fd718169d..4b8bf585f9ba 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmap; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; --=20 2.25.1