From nobody Sat Sep 21 09:53:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DABB9C47089 for ; Wed, 7 Dec 2022 09:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbiLGJtl (ORCPT ); Wed, 7 Dec 2022 04:49:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230210AbiLGJtf (ORCPT ); Wed, 7 Dec 2022 04:49:35 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AA522FA4A; Wed, 7 Dec 2022 01:49:34 -0800 (PST) X-UUID: 7015714541024174a3809cb6f43897b7-20221207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=z0BwPTiJq45XxbEGYv/PjtFL9GF0yWhObVdRootrVoo=; b=NZISzmMPCWLw+tiyDk2CvqgUXkLuboVppHNtIuf9e3DvOyWPImRq2U14cLm6MWuGjZ/+Js26SOBibJxuGO/zen9MvTQxQMLuvYRNe6oi2XmmC677jw7uIc5BuWpKnquwb5joZLyHBJIqSgTvqn8x1DO5vL3YPJn9ZPREF3/rBEw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:0d828875-3d90-46fd-9377-0b89f41d17dc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:e800ce16-b863-49f8-8228-cbdfeedd1fa4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 7015714541024174a3809cb6f43897b7-20221207 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 267878221; Wed, 07 Dec 2022 17:49:25 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 7 Dec 2022 17:49:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 7 Dec 2022 17:49:23 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: , , , , , Moudy Ho Subject: [PATCH v4 4/8] arm64: dts: mediatek: mt8195: add MUTEX configuration for VPPSYS Date: Wed, 7 Dec 2022 17:49:17 +0800 Message-ID: <20221207094921.15450-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221207094921.15450-1-moudy.ho@mediatek.com> References: <20221207094921.15450-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MT8195, the MMSYS has two Video Processor Pipepline Subsystems named VPPSYS0 and VPPSYS1, each with specific MUTEX to control Start of Frame(SOF) and End of Frame (EOF) signals. Before working with them, the addresses, interrupts, clocks and power domains need to be set up in dts. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index bd33b414c484..0ece3b46b66a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1639,6 +1639,15 @@ #clock-cells =3D <1>; }; =20 + mutex@1400f000 { + compatible =3D "mediatek,mt8195-vpp-mutex"; + reg =3D <0 0x1400f000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MUTEX>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { compatible =3D "mediatek,mt8195-smi-sub-common"; reg =3D <0 0x14010000 0 0x1000>; @@ -1745,6 +1754,15 @@ #clock-cells =3D <1>; }; =20 + mutex@14f01000 { + compatible =3D "mediatek,mt8195-vpp-mutex"; + reg =3D <0 0x14f01000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_DISP_MUTEX>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + larb5: larb@14f02000 { compatible =3D "mediatek,mt8195-smi-larb"; reg =3D <0 0x14f02000 0 0x1000>; --=20 2.18.0