From nobody Mon Nov 11 00:43:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CE40C352A1 for ; Wed, 7 Dec 2022 08:45:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229790AbiLGIpz (ORCPT ); Wed, 7 Dec 2022 03:45:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229971AbiLGIot (ORCPT ); Wed, 7 Dec 2022 03:44:49 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0C8632046; Wed, 7 Dec 2022 00:44:23 -0800 (PST) X-UUID: 14506489f95745dfa8715a7c33fd796b-20221207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Jb049zrd2hNJynQl+HJf/yYHcEbSdX0lcrbbz59HJmA=; b=Cut3aZSiJMaf3kxlJyax2pTx8NNcGdZ4hb4rCyvDh0krV+zciqxJ+6jh/MIJmN6DRNiXfHAKobuBC7Fy3x/8d5OeSUCVN6o3KZTETPHkZHX41wsRDMmCO51CB5zogXMxz1HwynHATL9UPrR3MEmxKAErvos4gnZYoy47oiPpva0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:a37d9037-a747-4f5e-9592-af7ce74ffda9,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.14,REQID:a37d9037-a747-4f5e-9592-af7ce74ffda9,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:dcaaed0,CLOUDID:4efacb16-b863-49f8-8228-cbdfeedd1fa4,B ulkID:221207164417AT5BLJI6,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 14506489f95745dfa8715a7c33fd796b-20221207 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 688031914; Wed, 07 Dec 2022 16:44:15 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 7 Dec 2022 16:44:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 7 Dec 2022 16:44:14 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: , , , , , Moudy Ho Subject: [PATCH v2 07/12] media: platform: mtk-mdp3: add checks for dummy components Date: Wed, 7 Dec 2022 16:44:07 +0800 Message-ID: <20221207084412.14075-8-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221207084412.14075-1-moudy.ho@mediatek.com> References: <20221207084412.14075-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some MDP3 components are only used as bridges and do not require configurat= ion. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 64 ++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index 365efe6a6c92..d22b6a62cf21 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -43,6 +43,13 @@ static bool is_output_disabled(int id, const struct img_= compparam *param, u32 co return (count < num) ? (dis_output || dis_tile) : true; } =20 +static bool is_dummy_engine(struct mdp_dev *mdp_dev, s32 inner_id) +{ + enum mtk_mdp_comp_id public_id =3D get_comp_public_id(mdp_dev, inner_id); + + return (mdp_dev->mdp_data->comp_data[public_id].match.type =3D=3D MDP_COM= P_TYPE_DUMMY); +} + static struct mtk_mutex *__get_mutex(const struct mdp_dev *mdp_dev, const struct mdp_pipe_info *p) { @@ -114,6 +121,12 @@ static int mdp_path_subfrm_require(const struct mdp_pa= th *path, =20 /* Set mutex mod */ for (index =3D 0; index < num_comp; index++) { + s32 inner_id =3D MDP_COMP_NONE; + + if (CFG_CHECK(MT8183, plat_id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; if (is_output_disabled(plat_id, ctx->param, count)) continue; @@ -138,6 +151,7 @@ static int mdp_path_subfrm_run(const struct mdp_path *p= ath, int index; u32 num_comp =3D 0; s32 event; + s32 inner_id =3D MDP_COMP_NONE; =20 if (-1 =3D=3D p->mutex_id) { dev_err(dev, "Incorrect mutex id"); @@ -150,6 +164,10 @@ static int mdp_path_subfrm_run(const struct mdp_path *= path, /* Wait WROT SRAM shared to DISP RDMA */ /* Clear SOF event for each engine */ for (index =3D 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; if (is_output_disabled(id, ctx->param, count)) continue; @@ -164,6 +182,10 @@ static int mdp_path_subfrm_run(const struct mdp_path *= path, =20 /* Wait SOF events and clear mutex modules (optional) */ for (index =3D 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; if (is_output_disabled(id, ctx->param, count)) continue; @@ -189,6 +211,12 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, stru= ct mdp_path *path) return -EINVAL; =20 for (index =3D 0; index < num_comp; index++) { + s32 inner_id =3D MDP_COMP_NONE; + + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; if (CFG_CHECK(MT8183, id)) param =3D (void *)CFG_ADDR(MT8183, path->config, components[index]); ret =3D mdp_comp_ctx_config(mdp, &path->comps[index], @@ -210,6 +238,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *= cmd, struct mdp_pipe_info pipe; int index, ret; u32 num_comp =3D 0; + s32 inner_id =3D MDP_COMP_NONE; =20 if (CFG_CHECK(MT8183, id)) num_comp =3D CFG_GET(MT8183, path->config, num_components); @@ -229,6 +258,10 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd = *cmd, } /* Config sub-frame information */ for (index =3D (num_comp - 1); index >=3D 0; index--) { + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; if (is_output_disabled(id, ctx->param, count)) continue; @@ -242,6 +275,10 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd = *cmd, return ret; /* Wait components done */ for (index =3D 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; if (is_output_disabled(id, ctx->param, count)) continue; @@ -251,6 +288,10 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd = *cmd, } /* Advance to the next sub-frame */ for (index =3D 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; ret =3D call_op(ctx, advance_subfrm, cmd, count); if (ret) @@ -274,6 +315,7 @@ static int mdp_path_config(struct mdp_dev *mdp, struct = mdp_cmdq_cmd *cmd, int index, count, ret; u32 num_comp =3D 0; u32 num_sub =3D 0; + s32 inner_id =3D MDP_COMP_NONE; =20 if (CFG_CHECK(MT8183, id)) num_comp =3D CFG_GET(MT8183, path->config, num_components); @@ -284,6 +326,10 @@ static int mdp_path_config(struct mdp_dev *mdp, struct= mdp_cmdq_cmd *cmd, /* Config path frame */ /* Reset components */ for (index =3D 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; ret =3D call_op(ctx, init_comp, cmd); if (ret) @@ -294,6 +340,11 @@ static int mdp_path_config(struct mdp_dev *mdp, struct= mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose; u32 out =3D 0; =20 + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; + if (CFG_CHECK(MT8183, id)) out =3D CFG_COMP(MT8183, ctx->param, outputs[0]); =20 @@ -312,6 +363,10 @@ static int mdp_path_config(struct mdp_dev *mdp, struct= mdp_cmdq_cmd *cmd, } /* Post processing information */ for (index =3D 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[index].type); + if (is_dummy_engine(path->mdp_dev, inner_id)) + continue; ctx =3D &path->comps[index]; ret =3D call_op(ctx, post_process, cmd); if (ret) @@ -512,9 +567,16 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq= _param *param) } cmdq_pkt_finalize(&cmd->pkt); =20 - for (i =3D 0; i < num_comp; i++) + for (i =3D 0; i < num_comp; i++) { + s32 inner_id =3D MDP_COMP_NONE; + + if (CFG_CHECK(MT8183, id)) + inner_id =3D CFG_GET(MT8183, path->config, components[i].type); + if (is_dummy_engine(mdp, inner_id)) + continue; memcpy(&comps[i], path->comps[i].comp, sizeof(struct mdp_comp)); + } =20 mdp->cmdq_clt->client.rx_callback =3D mdp_handle_cmdq_callback; cmd->mdp =3D mdp; --=20 2.18.0