From nobody Sat Sep 21 09:54:44 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC579C352A1 for ; Wed, 7 Dec 2022 08:46:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230071AbiLGIqG (ORCPT ); Wed, 7 Dec 2022 03:46:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229972AbiLGIov (ORCPT ); Wed, 7 Dec 2022 03:44:51 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B134532048; Wed, 7 Dec 2022 00:44:25 -0800 (PST) X-UUID: fd0bf8315ab8448c8226002c670ad8a0-20221207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MKF3IcNgWFgYyNMHk+O1vrqlypOAuQ2w+oXiFcFGlws=; b=FHZPGG+9J2h2UjefNTGD/EeE+SpvamweTsZjIl171/t3FAzX/oeYXeiYl2epJBeZO/j2CarE7wBjFZ8Xy3sU9La35na4hbxYD4PPRlz5yC15iCWYPb+iV13FEYTBu7wXaKuc9i9qqWMMXO4WJULHmKebIV7hzkm2VpzNKZAvGZM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:94cef7e6-f213-400f-a7a1-2e0477eb0736,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:4ffacb16-b863-49f8-8228-cbdfeedd1fa4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: fd0bf8315ab8448c8226002c670ad8a0-20221207 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1660161566; Wed, 07 Dec 2022 16:44:15 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 7 Dec 2022 16:44:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 7 Dec 2022 16:44:13 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: , , , , , Moudy Ho Subject: [PATCH v2 02/12] arm64: dts: mediatek: mt8195: add MDP3 nodes Date: Wed, 7 Dec 2022 16:44:02 +0800 Message-ID: <20221207084412.14075-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221207084412.14075-1-moudy.ho@mediatek.com> References: <20221207084412.14075-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 398 +++++++++++++++++++++++ 1 file changed, 398 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 0ece3b46b66a..556d2121d290 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1639,6 +1639,133 @@ #clock-cells =3D <1>; }; =20 + mdp3-rdma0@14001000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>, + <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_RDMA>, + <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP0>, + <&topckgen CLK_TOP_CFG_26M_VPP0>, + <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>, + <&vppsys0 CLK_VPP0_WARP0_RELAY>, + <&vppsys0 CLK_VPP0_WARP0_MDP_DL_ASYNC>, + <&vppsys0 CLK_VPP0_WARP1_ASYNC_TX>, + <&vppsys0 CLK_VPP0_WARP1_RELAY>, + <&vppsys0 CLK_VPP0_WARP1_MDP_DL_ASYNC>, + <&vppsys0 CLK_VPP0_VPP02VPP1_RELAY>, + <&vppsys1 CLK_VPP1_DL_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL_RELAY>, + <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>, + <&vppsys1 CLK_VPP1_SVPP2_VDO0_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP3_VDO1_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP2_VDO1_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP3_VDO0_DL_RELAY>; + mboxes =3D <&gce1 12 CMDQ_THR_PRIO_1>, + <&gce1 13 CMDQ_THR_PRIO_1>, + <&gce1 14 CMDQ_THR_PRIO_1>, + <&gce1 21 CMDQ_THR_PRIO_1>, + <&gce1 22 CMDQ_THR_PRIO_1>; + }; + + mdp3-fg0@14002000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_FG>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-stich0@14003000 { + compatible =3D "mediatek,mt8195-mdp3-stitch"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_STITCH>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-hdr0@14004000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_HDR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-aal0@14005000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-rsz0@14006000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RSZ>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-tdshp0@14007000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TDSHP>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-color0@14008000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14008000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-ovl0@14009000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14009000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-pad0@1400a000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_PADDING>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-tcc0@1400b000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TCC>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + mdp3-wrot0@1400c000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x1400c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys0 CLK_VPP0_MDP_WROT>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + mutex@1400f000 { compatible =3D "mediatek,mt8195-vpp-mutex"; reg =3D <0 0x1400f000 0 0x1000>; @@ -1787,6 +1914,277 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; }; =20 + mdp3-split0@14f06000 { + compatible =3D "mediatek,mt8195-mdp3-split"; + reg =3D <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>, + <&vppsys1 CLK_VPP1_DGI_IN>, + <&vppsys1 CLK_VPP1_DGI_OUT>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-tcc1@14f07000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x14f07000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-rdma1@14f08000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f08000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>, + <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-rdma2@14f09000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f09000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>, + <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-rdma3@14f0a000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f0a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + iommus =3D <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>, + <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-fg1@14f0b000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-fg2@14f0c000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-fg3@14f0d000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-hdr1@14f0e000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0e000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-hdr2@14f0f000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0f000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-hdr3@14f10000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f10000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-aal1@14f11000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f11000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-aal2@14f12000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f12000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-aal3@14f13000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f13000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-rsz1@14f14000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f14000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-rsz2@14f15000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f15000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>, + <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-rsz3@14f16000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f16000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>, + <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-tdshp1@14f17000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f17000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-tdshp2@14f18000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f18000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-tdshp3@14f19000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f19000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-merge0@14f1a000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-merge1@14f1b000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-color1@14f1c000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-color2@14f1d000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-color3@14f1e000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1e000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-ovl1@14f1f000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14f1f000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-pad1@14f20000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f20000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-pad2@14f21000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f21000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-pad3@14f22000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f22000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + mdp3-wrot1@14f23000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f23000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + imgsys: clock-controller@15000000 { compatible =3D "mediatek,mt8195-imgsys"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.18.0