From nobody Thu Sep 18 11:45:52 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E712CC4708E for ; Wed, 7 Dec 2022 11:56:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230228AbiLGL4L (ORCPT ); Wed, 7 Dec 2022 06:56:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229559AbiLGLza (ORCPT ); Wed, 7 Dec 2022 06:55:30 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ADA0DF09 for ; Wed, 7 Dec 2022 03:55:29 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id D64665C01EE; Wed, 7 Dec 2022 06:55:28 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Wed, 07 Dec 2022 06:55:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h=cc :cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1670414128; x= 1670500528; bh=8JXNhnLEO28YrVpxQj1wOWrxTedcnvz7vhR6KkgQoco=; b=R LmKnjjXZBm6rBghyUwCjAT9o/I/63f95yIyiAFZzYdCE9yrjv7mUtlipTewOb9eN wwafVTRbR4v/cMIdILFVBh4tTioq22RL4UoQMMG9Z9sEEoCO816NyJ/Qu5ab5LbW OxjdrT7QBHpuB1DHcfGbvF08MhJoq4n+hJB+CkLJRRw0Ks+HiWhIZ95n4oXSt3Be k5qCr4OTpDiq1Wr8xaaKNoUZF0Gfz2uJri5U80QcHlqv2xsFrpxPnAJpebP9b2Cj uNkfGN0V3VjtzWgpRemDiwN1+BkF9WAOh4PontCJBYGEIUZrIbfqm27M02r+Nvkv 5RZsuleR4K22SW0Y/rxqg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1670414128; x= 1670500528; bh=8JXNhnLEO28YrVpxQj1wOWrxTedcnvz7vhR6KkgQoco=; b=p Ft34ah9Fu13Yv7AllVsSCvN7m6JJvCKcAEa1SZoUh9WYB3PoqnvmJMAWNRxVCSiz hzHdS8iTSLCOxxeXL1OkLu+lFfwFX7puwMsSe2Ts1meus9Xpda+Fpg9P0AKRZ2ep t6ymLvKYz54w3ViQ8qYJEeINM5rFRdaHjvHEfE5yFTxb53dNqCvluTz/eOyGIFID Q/54PsDKnrvFr1etXD8b4qbWOv6XzpGCDvMooazvEL8f4wG7jEOLVIIDhsvweoRD zuIzGdt4/J+1ih+eI4VAuNghWEWv29H/Z0LrTnDqC+HJxAqQWn8sRXiU+zQr+DNp caIeYf25VY49y3q02IQBg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrudekgdefgecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhfffugggtgffkfhgjvfevofesthejredtredtjeenucfhrhhomhepofgrgihi mhgvucftihhprghrugcuoehmrgigihhmvgestggvrhhnohdrthgvtghhqeenucggtffrrg htthgvrhhnpeevvdelieejgedvkeffheekheeilefhgefgffehteekueelvddtueffheet ledtffenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhgrihhlfhhrohhmpe hmrgigihhmvgestggvrhhnohdrthgvtghh X-ME-Proxy: Feedback-ID: i8771445c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 7 Dec 2022 06:55:28 -0500 (EST) From: Maxime Ripard Date: Wed, 07 Dec 2022 12:53:20 +0100 Subject: [PATCH 09/15] drm/vc4: plane: Allow using 0 as a pixel order value MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221207-rpi-hvs-crtc-misc-v1-9-1f8e0770798b@cerno.tech> References: <20221207-rpi-hvs-crtc-misc-v1-0-1f8e0770798b@cerno.tech> In-Reply-To: <20221207-rpi-hvs-crtc-misc-v1-0-1f8e0770798b@cerno.tech> To: Emma Anholt , Maxime Ripard , David Airlie , Daniel Vetter , Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Mateusz Kwiatkowski , Maxime Ripard X-Mailer: b4 0.11.0-dev-8c583 X-Developer-Signature: v=1; a=openpgp-sha256; l=3691; i=maxime@cerno.tech; h=from:subject:message-id; bh=D88ulcoenFvBXOL7I0IQHsqV5VXn1HkB+dnvXbQe7Wg=; b=owGbwMvMwCX2+D1vfrpE4FHG02pJDMkT6lZ+5nstOE3Avry7+Leqn7ulwv2rVWoH/igtP9EcmTVL 50NJRykLgxgXg6yYIkuMsPmSuFOzXney8c2DmcPKBDKEgYtTACayTpyR4UdEs8CS2R6suke1ntu4P/ vFMWPWxdhTC6dtT2mwbU/0L2P4n6acL/dvQr5lS7GhQN9KqfCCfkmROO0bh59FBnb0SlWxAQA= X-Developer-Key: i=maxime@cerno.tech; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dave Stevenson vc4_plane_mode_set for HVS5 was using pixel_order unless pixel_order_hvs5 was non-zero, except 0 is a valid value for the pixel_order. Specify pixel_order_hvs5 for all formats and remove the conditional. Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_plane.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plan= e.c index eb0ac2167937..8b4805c937f0 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -65,11 +65,13 @@ static const struct hvs_format { .drm =3D DRM_FORMAT_RGB565, .hvs =3D HVS_PIXEL_FORMAT_RGB565, .pixel_order =3D HVS_PIXEL_ORDER_XRGB, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XRGB, }, { .drm =3D DRM_FORMAT_BGR565, .hvs =3D HVS_PIXEL_FORMAT_RGB565, .pixel_order =3D HVS_PIXEL_ORDER_XBGR, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XBGR, }, { .drm =3D DRM_FORMAT_ARGB1555, @@ -87,56 +89,67 @@ static const struct hvs_format { .drm =3D DRM_FORMAT_RGB888, .hvs =3D HVS_PIXEL_FORMAT_RGB888, .pixel_order =3D HVS_PIXEL_ORDER_XRGB, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XRGB, }, { .drm =3D DRM_FORMAT_BGR888, .hvs =3D HVS_PIXEL_FORMAT_RGB888, .pixel_order =3D HVS_PIXEL_ORDER_XBGR, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XBGR, }, { .drm =3D DRM_FORMAT_YUV422, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCBCR, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCBCR, }, { .drm =3D DRM_FORMAT_YVU422, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCRCB, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCRCB, }, { .drm =3D DRM_FORMAT_YUV420, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCBCR, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCBCR, }, { .drm =3D DRM_FORMAT_YVU420, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCRCB, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCRCB, }, { .drm =3D DRM_FORMAT_NV12, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCBCR, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCBCR, }, { .drm =3D DRM_FORMAT_NV21, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCRCB, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCRCB, }, { .drm =3D DRM_FORMAT_NV16, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCBCR, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCBCR, }, { .drm =3D DRM_FORMAT_NV61, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, .pixel_order =3D HVS_PIXEL_ORDER_XYCRCB, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCRCB, }, { .drm =3D DRM_FORMAT_P030, .hvs =3D HVS_PIXEL_FORMAT_YCBCR_10BIT, .pixel_order =3D HVS_PIXEL_ORDER_XYCBCR, + .pixel_order_hvs5 =3D HVS_PIXEL_ORDER_XYCBCR, .hvs5_only =3D true, }, { @@ -1031,15 +1044,10 @@ static int vc4_plane_mode_set(struct drm_plane *pla= ne, vc4_dlist_write(vc4_state, 0xc0c0c0c0); =20 } else { - u32 hvs_pixel_order =3D format->pixel_order; - - if (format->pixel_order_hvs5) - hvs_pixel_order =3D format->pixel_order_hvs5; - /* Control word */ vc4_dlist_write(vc4_state, SCALER_CTL0_VALID | - (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) | + (format->pixel_order_hvs5 << SCALER_CTL0_ORDER_SHIFT) | (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | (vc4_state->is_unity ? --=20 2.38.1