From nobody Thu Sep 18 11:26:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E06C6C4708E for ; Tue, 6 Dec 2022 12:57:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234822AbiLFM5E (ORCPT ); Tue, 6 Dec 2022 07:57:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234724AbiLFM4v (ORCPT ); Tue, 6 Dec 2022 07:56:51 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BF7A26AE5 for ; Tue, 6 Dec 2022 04:56:43 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id n21so5911916ejb.9 for ; Tue, 06 Dec 2022 04:56:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HyTsVNX7Hzgy2yuFXUB0FPuyNnjByEWV/KA5BFtfNhA=; b=Qd/GL1MHeXgLbMYyUrp+KBSyKHgcTmuslNeiJrh5b+znPB3XYt63cr/RFYF+WuF7rZ OEHIlFQ69Ace+DlLbnFut+BIZEqRWKnZmMEz9bmMWf3256ta1OlfM+lHa7apP0mi5wzO Tsm6MHmFHRnH4mjAJbKkX/7m8wsxAoWAVCEdua69zcgLjsSeFafVJJp1RZPZhy9qkBPJ kkgf3ydJjFpeeYFgObKDZrcC5RHeQYIxzuHMgJ7xnMvCUhdvzpf6uXK9yWPcrsyxoMIb m47WvKOCFwIWUN6NFZYt9mA5j0RglquttEcdDKT9D5wKpU7kfjO3V+39MB1wIAtAIumB CjVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HyTsVNX7Hzgy2yuFXUB0FPuyNnjByEWV/KA5BFtfNhA=; b=SzdVkHssznQfHW5w+4YW4VvbwSLE5rIYR8o/JMrqaQ/HrVcStwiGxlp1MIFo7o4qxK 8GEVe6briSMFxSpWGEQIXPu1/qhTen3d7VQEdy7TpYhyZsGF5zZONU6BABBPzBTq98Mh HjqzwsTosO4DfYAcwQ7bXvqxIojpTH8udl+o7Snel2PDFqK6Y/BYNNanOQ82cCGVLS7t 39z3NTSyXBtC1ZCgkmaGM1KWwJEYnWkhNQb9Yl8Mws8Qt/HqtWdOdSMKSi1/C2hj31dm XZsa56F1eid9J/xcj/BT/dW33daySw6fLdpFwwasKyIV4H13Or2ST5gpHAMZqGFVK2Lb Mc2A== X-Gm-Message-State: ANoB5pnG8uwf/VRt+80nhcgOUg02CEviotUGIuQ85JCWisjBqMvqjPiy LblGVRoI7qcenFpQBgyjJwhFJQ== X-Google-Smtp-Source: AA0mqf7rdk8nLt+qOEFE34vE9G05Qz+fl3SvjUNHtgAkNNEApCI1VSmLWrYBpqMjvO2Tq4Gyan0erA== X-Received: by 2002:a17:906:1484:b0:7ae:6746:f270 with SMTP id x4-20020a170906148400b007ae6746f270mr23036100ejc.728.1670331401625; Tue, 06 Dec 2022 04:56:41 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id v15-20020aa7cd4f000000b0046150ee13besm932991edw.65.2022.12.06.04.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 04:56:41 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 1/5] dt-bindings: clock: Add SM8550 TCSR CC clocks Date: Tue, 6 Dec 2022 14:56:31 +0200 Message-Id: <20221206125635.952114-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206125635.952114-1-abel.vesa@linaro.org> References: <20221206125635.952114-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcs= r.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 000000000000..15176b0457d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h + +properties: + compatible: + const: qcom,sm8550-tcsr + + clocks: + items: + - description: Board XO source + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1fc0000 { + compatible =3D "qcom,sm8550-tcsr"; + reg =3D <0x1fc0000 0x30000>; + clocks =3D <&rpmhcc RPMH_CXO_PAD_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bind= ings/clock/qcom,sm8550-tcsr.h new file mode 100644 index 000000000000..091cb76f953a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif --=20 2.34.1 From nobody Thu Sep 18 11:26:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FE32C4708E for ; Tue, 6 Dec 2022 12:57:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234879AbiLFM5H (ORCPT ); Tue, 6 Dec 2022 07:57:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234773AbiLFM4x (ORCPT ); Tue, 6 Dec 2022 07:56:53 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ED4C634B for ; Tue, 6 Dec 2022 04:56:44 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id n21so5912071ejb.9 for ; Tue, 06 Dec 2022 04:56:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BhLdyy64MSy62j2GfoCPYL31V7FQmGy5yzQrHHdIKxE=; b=g6HBJJPsPgFds3XaK3M7z/BvudPRUcwGtnL+oGDlDvXOtEkoMuNAqHl3OMAzl4fuFe TFqtqcUHNJqrvW0ZA42/LTF/SV0ohoD7HOMyLWBwm6XocA19Vm6l25myvfDRxNZoKoNa 9WDR/piOmCw7M1LLk08FMGO3Uo+ZvUZJutsmGw434YVhQcm2FglR3oNHQ9TEKJvahZZf dP44i+6tzmLQ/BCxGD+TBocovqirmlrTmW0+C/7EOacWibFe/K/jOelXVFa3ruLNhKCL tbgfDobKu9xi/qtChY3A2RiBWKdNl52/0ldEvKFk8oBsCtUK/4U1hhcWZ036wI//F0UH 8FEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BhLdyy64MSy62j2GfoCPYL31V7FQmGy5yzQrHHdIKxE=; b=bRiolQydN5DxBuS7Es5roRTOTg/cjSufQohtnmhft5aLXxDDnR9QdYIcWgyIUqecyi xe+xg7Uu/ucBzqn7PI87Z4B0elpyAKbiMfrfxPE+QtQZ9OB5/7/o12rGua6obppvRom/ eWtnQ/QT1rQDi47M8Dr2mSFwGpAuZsW936AArC76xac5fwKVaPZuH1KdNeJYR7HsC5LL xB4LX3urRx7DtfJhG9sIkIT/Tm2PNwISLTiVG2yuQY4/cAuxBupokY08ub1JkT7It11e nVqpKfM2mmbcFvjtWM4NesIEPAYdbkOBFnQhyTyUUR3tSVcHSwCkuVIEKZ/BVuNqymQj +mTQ== X-Gm-Message-State: ANoB5pleVxGOS1gI9IY0WzicYOwbDi+bbfw6LoTISaID3/xClGc2wfRx Asn+y+UvlwTGnMafzEcPlivmvQ== X-Google-Smtp-Source: AA0mqf784LtVQVhnatJbwdOS+3gZ3Qlr9+4yvGwMeDmOskexJXEozG/+Iq3YbBEwyWqDF7HqnySd+w== X-Received: by 2002:a17:906:2cd3:b0:7bf:b675:ffdd with SMTP id r19-20020a1709062cd300b007bfb675ffddmr33116400ejr.610.1670331403050; Tue, 06 Dec 2022 04:56:43 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id v15-20020aa7cd4f000000b0046150ee13besm932991edw.65.2022.12.06.04.56.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 04:56:42 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 2/5] dt-bindings: clock: Add RPMHCC for SM8550 Date: Tue, 6 Dec 2022 14:56:32 +0200 Message-Id: <20221206125635.952114-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206125635.952114-1-abel.vesa@linaro.org> References: <20221206125635.952114-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings and update documentation for clock rpmh driver on SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index fccb91e78e49..b405da7700be 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk =20 clocks: maxItems: 1 --=20 2.34.1 From nobody Thu Sep 18 11:26:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D518CC47090 for ; Tue, 6 Dec 2022 12:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234973AbiLFM5R (ORCPT ); Tue, 6 Dec 2022 07:57:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234859AbiLFM47 (ORCPT ); Tue, 6 Dec 2022 07:56:59 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19F762A25C for ; Tue, 6 Dec 2022 04:56:46 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id m18so4409674eji.5 for ; Tue, 06 Dec 2022 04:56:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=quL6WPeERZYedqB/nklThp0WUV+KiBC4sy50mhyRH+A=; b=ZidEHgzTJHJ971XlhxbwNqDseoGZb4yiXfiNEuK1MupurvPx4WxIuPhAO1Ol8lRoFB rElAMvO2HZedoExmb3Hv0y7cyO6c2VkfegW235AT0hMt1ZXIEpnTLorrH8w3T5TSHVnY 8LrwsV6Xp3Z6PHjS2Lyosfj7Oy4ekiglnkuiRZAxkgHj/95kuz9J90cbAYVULc8TbR7N atcACt5TV6g0ZtVipPTrK+FcvpMHZf3D776wmsWMZJ5NUdY46L5N3cchWtN9xB23qWow E3O92JC0A5ANdgWI0Ji5KwDIcbWLxPUyat8dGbma4FPZN6SUORykLq9eKEqk2uT6TO5w 5bFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=quL6WPeERZYedqB/nklThp0WUV+KiBC4sy50mhyRH+A=; b=6bTgCsdYK1mS+G1b8pXxTqIkJmPayOiGTM1xUCkgB73jr2gJWt+ls+Y7p3yNhbai/g y70JVVchmjFtAzwdN4jtm83AqJBS0m9cg0gNuL/feVmZTPsOgQ+4H73LAhdy+NygiHcv MugNpN1Mz2h9QLQH3slopdP1w8NxCrcxlp6xCFq6CqX1leurIPQlhBBubtzwh6aTfcmO TMqJTLDG2ATGIk7gwzP0sxoJlnpFnke/spRF3Sf530yTEdiqCTLza0qH9BqnJob34jwu HeiDOMyDH3sc06V1f+LKYK7xcgZeresiR1jDVUVydOCDNWsnx44kZGgJcynVrPUmE3SJ DfoA== X-Gm-Message-State: ANoB5pnTlP8A/8ZfXNihhS6JlJqKeApS6IVMRzfnJRCLa2PWQVMbg02j qeRtZmFRAl41Fejr4ExsHu5kucGyfGXZmp86 X-Google-Smtp-Source: AA0mqf67q3Yvp7TQgfE72/7Tj0luKiaE0vPffE6fFIVzoJ1X9eDGj9MyzYpyk5HclUqH1c7klkS7AA== X-Received: by 2002:a17:907:3f8a:b0:7bf:4ae6:c36 with SMTP id hr10-20020a1709073f8a00b007bf4ae60c36mr35871464ejc.674.1670331404524; Tue, 06 Dec 2022 04:56:44 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id v15-20020aa7cd4f000000b0046150ee13besm932991edw.65.2022.12.06.04.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 04:56:44 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 3/5] dt-bindings: clock: qcom,rpmh: Add CXO PAD clock IDs Date: Tue, 6 Dec 2022 14:56:33 +0200 Message-Id: <20221206125635.952114-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206125635.952114-1-abel.vesa@linaro.org> References: <20221206125635.952114-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SM8550 has a new fixed divider as child clock of CXO called CXO_PAD, so add IDs for it. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,rpmh.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/cl= ock/qcom,rpmh.h index 0a7d1be0d124..f3e0288420ce 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -33,5 +33,7 @@ #define RPMH_HWKM_CLK 24 #define RPMH_QLINK_CLK 25 #define RPMH_QLINK_CLK_A 26 +#define RPMH_CXO_PAD_CLK 27 +#define RPMH_CXO_PAD_CLK_A 28 =20 #endif --=20 2.34.1 From nobody Thu Sep 18 11:26:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93F9BC4708E for ; Tue, 6 Dec 2022 12:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234891AbiLFM5Y (ORCPT ); Tue, 6 Dec 2022 07:57:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234794AbiLFM5C (ORCPT ); Tue, 6 Dec 2022 07:57:02 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88E3D9FC5 for ; Tue, 6 Dec 2022 04:56:47 -0800 (PST) Received: by mail-ed1-x52c.google.com with SMTP id i15so11946559edf.2 for ; Tue, 06 Dec 2022 04:56:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xGLwUiqnWNNCSh7SfaJVMgmwcN3tXBqQdd3/EujPmbQ=; b=BLvjAc5qaWMqqX0LcNFZyaPScS8Auq+3la+ia6AMIs5X41daPyVN7wWTB2K6uBVJNg eQ5nU2q+rxJ/soT09N7oSzhTLMOu8Kh8TL0BXSBzZ3ERRcqvyqekAeyjnPbFsJcH9b1w bEj4b2GjZocjwIk5jbgIjaxUyAKEFj7d9K27jW3pPQ9xUgDwXyLjOX7rJZ1K6BaLn6Fo 2zgsy2KnfHOco82Q1tx7xonCspRrejUD3mA9xa2Ek88xJwDfE59ePdH9GogZBz5vma5W Vrl2yN1LFxZ1hM7L1lJf60Pe+U9clI2sr7jP+BFBkPjtAnA4fP3zapyoex1Os/Jj/6i/ xqWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xGLwUiqnWNNCSh7SfaJVMgmwcN3tXBqQdd3/EujPmbQ=; b=XqbZOxt1Jg1qKzu5UeRjzq2dZlI/UIwuMWeksiiuPTK8J5woIqGUnovDBNytElBgz2 g7+TCHdnEZLrPTYiqoOqW/yLb9DU/CQcgRgIdNrcVyhTfmeQRs7nID7+oI/dBNDh8wkO GedgG/4lWNlEY9E5hgk7u39EQxk8eUepQq/UkFeFv8FbwtP8lEYjOlvKxK8X7G+8n6lJ YD6F2mht7F9Pu3BuuaZLKRSREomqjOeLInlKnKKmSzqRdKw25Ukec2x3yXW4oHmxOFK4 AzaluEs9Uc9Ld3JdSx23b1x9BOjFFEQmG2vGnJ82VpZM6LqctfDYc59o264nVuvd20Be cldQ== X-Gm-Message-State: ANoB5pk5f4I0dDwKzayv2xbYhuXk1lX2TkelcjMB/6YM+9Kt3bU4iQU9 fwy8mRKWtYMGqP8eaDuXrp1+gw== X-Google-Smtp-Source: AA0mqf7/OHiK8cWKxQjLJ0SL7h+aSGvGW7e1tYw7TFeyR6QAAaQMDsaQ0v27h441WmswYjKWqOYrog== X-Received: by 2002:a05:6402:4d6:b0:458:789b:c1b0 with SMTP id n22-20020a05640204d600b00458789bc1b0mr65538122edw.89.1670331405860; Tue, 06 Dec 2022 04:56:45 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id v15-20020aa7cd4f000000b0046150ee13besm932991edw.65.2022.12.06.04.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 04:56:45 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 4/5] clk: qcom: rpmh: Add support for SM8550 rpmh clocks Date: Tue, 6 Dec 2022 14:56:34 +0200 Message-Id: <20221206125635.952114-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206125635.952114-1-abel.vesa@linaro.org> References: <20221206125635.952114-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds the RPMH clocks present in SM8550 SoC. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 110 +++++++++++++++++++++++++++++------- 1 file changed, 90 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 2c2ef4b6d130..ce81c76ed0fd 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -130,6 +130,34 @@ static DEFINE_MUTEX(rpmh_clk_lock); }, \ } =20 +#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, _div) \ + static struct clk_fixed_factor clk_fixed_factor##_##_name =3D { \ + .mult =3D 1, \ + .div =3D _div, \ + .hw.init =3D &(struct clk_init_data){ \ + .ops =3D &clk_fixed_factor_ops, \ + .name =3D #_name, \ + .parent_data =3D &(const struct clk_parent_data){ \ + .fw_name =3D #_parent_name, \ + .name =3D #_parent_name, \ + }, \ + .num_parents =3D 1, \ + }, \ + }; \ + static struct clk_fixed_factor clk_fixed_factor##_##_name##_ao =3D { \ + .mult =3D 1, \ + .div =3D _div, \ + .hw.init =3D &(struct clk_init_data){ \ + .ops =3D &clk_fixed_factor_ops, \ + .name =3D #_name "_ao", \ + .parent_data =3D &(const struct clk_parent_data){ \ + .fw_name =3D #_parent_name "_ao", \ + .name =3D #_parent_name "_ao", \ + }, \ + .num_parents =3D 1, \ + }, \ + } + static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) { return container_of(_hw, struct clk_rpmh, hw); @@ -345,6 +373,8 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); =20 +DEFINE_CLK_FIXED_FACTOR(bi_tcxo_div2, bi_tcxo, 2); + DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); @@ -366,6 +396,16 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); =20 +DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); +DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); +DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); +DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); +DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); + +DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); +DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); +DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); + DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); =20 DEFINE_CLK_RPMH_BCM(ce, "CE0"); @@ -576,6 +616,33 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 =3D { .num_clks =3D ARRAY_SIZE(sm8450_rpmh_clocks), }; =20 +static struct clk_hw *sm8550_rpmh_clocks[] =3D { + [RPMH_CXO_PAD_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_PAD_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_CXO_CLK] =3D &clk_fixed_factor_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_fixed_factor_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] =3D &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] =3D &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK2] =3D &clk_rpmh_clk7_a2.hw, + [RPMH_LN_BB_CLK2_A] =3D &clk_rpmh_clk7_a2_ao.hw, + [RPMH_LN_BB_CLK3] =3D &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] =3D &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK1] =3D &clk_rpmh_clk1_a1.hw, + [RPMH_RF_CLK1_A] =3D &clk_rpmh_clk1_a1_ao.hw, + [RPMH_RF_CLK2] =3D &clk_rpmh_clk2_a1.hw, + [RPMH_RF_CLK2_A] =3D &clk_rpmh_clk2_a1_ao.hw, + [RPMH_RF_CLK3] =3D &clk_rpmh_clk3_a1.hw, + [RPMH_RF_CLK3_A] =3D &clk_rpmh_clk3_a1_ao.hw, + [RPMH_RF_CLK4] =3D &clk_rpmh_clk4_a1.hw, + [RPMH_RF_CLK4_A] =3D &clk_rpmh_clk4_a1_ao.hw, + [RPMH_IPA_CLK] =3D &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm8550 =3D { + .clks =3D sm8550_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(sm8550_rpmh_clocks), +}; + static struct clk_hw *sc7280_rpmh_clocks[] =3D { [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div4_ao.hw, @@ -683,29 +750,31 @@ static int clk_rpmh_probe(struct platform_device *pde= v) =20 name =3D hw_clks[i]->init->name; =20 - rpmh_clk =3D to_clk_rpmh(hw_clks[i]); - res_addr =3D cmd_db_read_addr(rpmh_clk->res_name); - if (!res_addr) { - dev_err(&pdev->dev, "missing RPMh resource address for %s\n", - rpmh_clk->res_name); - return -ENODEV; - } + if (hw_clks[i]->init->ops !=3D &clk_fixed_factor_ops) { + rpmh_clk =3D to_clk_rpmh(hw_clks[i]); + res_addr =3D cmd_db_read_addr(rpmh_clk->res_name); + if (!res_addr) { + dev_err(&pdev->dev, "missing RPMh resource address for %s\n", + rpmh_clk->res_name); + return -ENODEV; + } =20 - data =3D cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); - if (IS_ERR(data)) { - ret =3D PTR_ERR(data); - dev_err(&pdev->dev, - "error reading RPMh aux data for %s (%d)\n", - rpmh_clk->res_name, ret); - return ret; - } + data =3D cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); + if (IS_ERR(data)) { + ret =3D PTR_ERR(data); + dev_err(&pdev->dev, + "error reading RPMh aux data for %s (%d)\n", + rpmh_clk->res_name, ret); + return ret; + } =20 - /* Convert unit from Khz to Hz */ - if (aux_data_len =3D=3D sizeof(*data)) - rpmh_clk->unit =3D le32_to_cpu(data->unit) * 1000ULL; + /* Convert unit from Khz to Hz */ + if (aux_data_len =3D=3D sizeof(*data)) + rpmh_clk->unit =3D le32_to_cpu(data->unit) * 1000ULL; =20 - rpmh_clk->res_addr +=3D res_addr; - rpmh_clk->dev =3D &pdev->dev; + rpmh_clk->res_addr +=3D res_addr; + rpmh_clk->dev =3D &pdev->dev; + } =20 ret =3D devm_clk_hw_register(&pdev->dev, hw_clks[i]); if (ret) { @@ -741,6 +810,7 @@ static const struct of_device_id clk_rpmh_match_table[]= =3D { { .compatible =3D "qcom,sm8250-rpmh-clk", .data =3D &clk_rpmh_sm8250}, { .compatible =3D "qcom,sm8350-rpmh-clk", .data =3D &clk_rpmh_sm8350}, { .compatible =3D "qcom,sm8450-rpmh-clk", .data =3D &clk_rpmh_sm8450}, + { .compatible =3D "qcom,sm8550-rpmh-clk", .data =3D &clk_rpmh_sm8550}, { .compatible =3D "qcom,sc7280-rpmh-clk", .data =3D &clk_rpmh_sc7280}, { } }; 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Tue, 06 Dec 2022 04:56:47 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id v15-20020aa7cd4f000000b0046150ee13besm932991edw.65.2022.12.06.04.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 04:56:46 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 5/5] clk: qcom: Add TCSR clock driver for SM8550 Date: Tue, 6 Dec 2022 14:56:35 +0200 Message-Id: <20221206125635.952114-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206125635.952114-1-abel.vesa@linaro.org> References: <20221206125635.952114-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The TCSR clock controller found on SM8550 provides refclks for PCIE, USB and UFS. Add clock driver for it. This patch is based on initial code downstream. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 7 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-sm8550.c | 192 +++++++++++++++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 drivers/clk/qcom/tcsrcc-sm8550.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 70d43f0a8919..b9f5505d68f0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -797,6 +797,13 @@ config SM_GPUCC_8350 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_TCSRCC_8550 + tristate "SM8550 TCSR Clock Controller" + select QCOM_GDSC + help + Support for the TCSR clock controller on SM8550 devices. + Say Y if you want to use peripheral devices such as SD/UFS. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f18c446a97ea..f5ce429c724c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GPUCC_6350) +=3D gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) +=3D gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) +=3D gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o +obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8150) +=3D videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8= 550.c new file mode 100644 index 000000000000..2c67ee71c196 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_pcie_0_clkref_en =3D { + .halt_reg =3D 0x15100, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x15100, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "tcsr_pcie_0_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_1_clkref_en =3D { + .halt_reg =3D 0x15114, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x15114, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "tcsr_pcie_1_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en =3D { + .halt_reg =3D 0x15110, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x15110, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "tcsr_ufs_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_pad_clkref_en =3D { + .halt_reg =3D 0x15104, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x15104, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "tcsr_ufs_pad_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_clkref_en =3D { + .halt_reg =3D 0x15118, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x15118, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "tcsr_usb2_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_clkref_en =3D { + .halt_reg =3D 0x15108, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x15108, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "tcsr_usb3_clkref_en", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO_PAD, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_sm8550_clocks[] =3D { + [TCSR_PCIE_0_CLKREF_EN] =3D &tcsr_pcie_0_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] =3D &tcsr_ufs_clkref_en.clkr, + [TCSR_UFS_PAD_CLKREF_EN] =3D &tcsr_ufs_pad_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] =3D &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] =3D &tcsr_usb3_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_sm8550_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x2f000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc tcsr_cc_sm8550_desc =3D { + .config =3D &tcsr_cc_sm8550_regmap_config, + .clks =3D tcsr_cc_sm8550_clocks, + .num_clks =3D ARRAY_SIZE(tcsr_cc_sm8550_clocks), +}; + +static const struct of_device_id tcsr_cc_sm8550_match_table[] =3D { + { .compatible =3D "qcom,sm8550-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table); + +static int tcsr_cc_sm8550_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &tcsr_cc_sm8550_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap); +} + +static struct platform_driver tcsr_cc_sm8550_driver =3D { + .probe =3D tcsr_cc_sm8550_probe, + .driver =3D { + .name =3D "tcsr_cc-sm8550", + .of_match_table =3D tcsr_cc_sm8550_match_table, + }, +}; + +static int __init tcsr_cc_sm8550_init(void) +{ + return platform_driver_register(&tcsr_cc_sm8550_driver); +} +subsys_initcall(tcsr_cc_sm8550_init); + +static void __exit tcsr_cc_sm8550_exit(void) +{ + platform_driver_unregister(&tcsr_cc_sm8550_driver); +} +module_exit(tcsr_cc_sm8550_exit); + +MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1