From nobody Sat Sep 21 07:31:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CBA6C352A1 for ; Tue, 6 Dec 2022 11:24:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234655AbiLFLXw (ORCPT ); Tue, 6 Dec 2022 06:23:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234051AbiLFLXk (ORCPT ); Tue, 6 Dec 2022 06:23:40 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61F4410D1; Tue, 6 Dec 2022 03:23:38 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9A13E6602AB7; Tue, 6 Dec 2022 11:23:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1670325817; bh=BVRfMtyMwCW0uJUlIomeaMSMRsqv9hI5Ac5ZtARAL88=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D0iDqCNMaVr/fLBzKRLQ2q8AeNqg1INofHA1m2ml76G9DY5GIU+mk7za6818i3ruS V3hVuskVftUjbI8eKKZy6OXUBlW4ZnzjoGvS2lk93lVrvYxw3d8mFj4DN5Y80XjKpp qQyVUcTB7lCoylb/H3TFkKxSsdvmlkVDC4Lzaajo0D6sWJCDB+8EqurFpvUeToCclX lZATARRI5zFy5cJJ6sPGXkmTDOOPhSLjJQyko0e9XzlX1U0o3y7O9eKB+mUqfQpXIb tPacq6AVDVWQ462Oe9FVEcnVFc9ADgc88/Y5jHZ7XlUsmbGEEhewHWRdM1GVEv3GwM kA/oxc5rSgCbg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, nfraprado@collabora.com, kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 1/5] arm64: dts: mt8195: Add complete CPU caches information Date: Tue, 6 Dec 2022 12:23:26 +0100 Message-Id: <20221206112330.78431-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> References: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This SoC features two clusters composed of: - 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 4x Cortex A78: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 2MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 5d31536f4c48..539c49324d64 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -39,6 +39,12 @@ cpu0: cpu@0 { clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <308>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -52,6 +58,12 @@ cpu1: cpu@100 { clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <308>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -65,6 +77,12 @@ cpu2: cpu@200 { clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <308>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -78,6 +96,12 @@ cpu3: cpu@300 { clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <308>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -91,6 +115,12 @@ cpu4: cpu@400 { clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; @@ -104,6 +134,12 @@ cpu5: cpu@500 { clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; @@ -117,6 +153,12 @@ cpu6: cpu@600 { clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; @@ -130,6 +172,12 @@ cpu7: cpu@700 { clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; @@ -215,18 +263,28 @@ cluster_off_b: cluster-off-b { l2_0: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; next-level-cache =3D <&l3_0>; }; =20 l2_1: l2-cache1 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <262144>; + cache-line-size =3D <64>; + cache-sets =3D <512>; next-level-cache =3D <&l3_0>; }; =20 l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; + cache-size =3D <2097152>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; }; }; =20 --=20 2.38.1 From nobody Sat Sep 21 07:31:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC9ADC4708C for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1670325817; bh=lO17/VleyNXgn9N/3LZMvXR6w59EZEPe9elRRz8H1Oo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BdcQBBpB7uwn4qOnYraSkpv3u0Rp+4xUnwnIUbUKeHhu7LssAJ5DJCM/iTCIm2Hz9 7/6YVhx+kJQbpI0Yd18SBhBOWmXav4RkIJPS6ohsQBNnLOYAoa2xtX5c+bA66tWeNb 7Q5mmtcKcYgbo5PihT7jMI3IapID34FEGhRX+6AxEQs/k5OnwFoKwnLJlLGTFLJhot pzyFZaVbO7tC/nrluuNezvh25jai0uXRiKRIF3JyrdnKARTC7z1njEmRSBl3sEbIcr UnQmuFm5cTZ9I8soWXtAP5ngp+V8Mm7zDTyFILMtpXLwY/r7nEar14Jmav80gxNPG+ VZayvKqB5NSSw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, nfraprado@collabora.com, kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 2/5] arm64: dts: mt8192: Add complete CPU caches information Date: Tue, 6 Dec 2022 12:23:27 +0100 Message-Id: <20221206112330.78431-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> References: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This SoC features two clusters composed of: - 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 4x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 2MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 424fc89cc6f7..3b5d49bf174d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -54,6 +54,12 @@ cpu0: cpu@0 { enable-method =3D "psci"; clock-frequency =3D <1701000000>; cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; }; @@ -65,6 +71,12 @@ cpu1: cpu@100 { enable-method =3D "psci"; clock-frequency =3D <1701000000>; cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; }; @@ -76,6 +88,12 @@ cpu2: cpu@200 { enable-method =3D "psci"; clock-frequency =3D <1701000000>; cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; }; @@ -87,6 +105,12 @@ cpu3: cpu@300 { enable-method =3D "psci"; clock-frequency =3D <1701000000>; cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; }; @@ -98,6 +122,12 @@ cpu4: cpu@400 { enable-method =3D "psci"; clock-frequency =3D <2171000000>; cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; }; @@ -109,6 +139,12 @@ cpu5: cpu@500 { enable-method =3D "psci"; clock-frequency =3D <2171000000>; cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; }; @@ -120,6 +156,12 @@ cpu6: cpu@600 { enable-method =3D "psci"; clock-frequency =3D <2171000000>; cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; }; @@ -131,6 +173,12 @@ cpu7: cpu@700 { enable-method =3D "psci"; clock-frequency =3D <2171000000>; cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; }; @@ -170,18 +218,28 @@ core3 { l2_0: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; next-level-cache =3D <&l3_0>; }; =20 l2_1: l2-cache1 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <262144>; + cache-line-size =3D <64>; + cache-sets =3D <512>; next-level-cache =3D <&l3_0>; }; =20 l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; + cache-size =3D <2097152>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; }; =20 idle-states { --=20 2.38.1 From nobody Sat Sep 21 07:31:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C18C4C47090 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1670325818; bh=rlTgEOFncee6fPGxGrdmPJK4iALNYJfpw5aOcS2FPzc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iI84tUNJ2OgxuFKyUIzMasbWPp2x5Gvjz71MPz5WLHgrr45NUIS3ZkaYJPU9r9nmn tyvLjCHa52c0d8hIvlGd/aAyUeE7epONddmSG+W201MlMM9sJrlHIQ/4G+wWvBG+yc Dhj+aYvpt1aRuXYXZrV1z+2FHquB2R7O7eDDO4xvtlH0EzvLKtT/0+ePpShU4MPNi6 1V+g68BhgCE7uGuG+ueWHd8B7hVHlE6wbaazQ3BoL5NMI+S9gB4x0XqjiyuhgmYjI6 TgcFVHcJL89VE2I7qWRPU0DXg/BTDRUHuPwiz9UhfYoiglXrmuZCwtUH942k9m+VUa UoYC7CAvWdaFA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, nfraprado@collabora.com, kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 3/5] arm64: dts: mt8186: Add complete CPU caches information Date: Tue, 6 Dec 2022 12:23:28 +0100 Message-Id: <20221206112330.78431-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> References: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This SoC features two clusters composed of: - 6x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 2x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 1MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 4a2f7ad3c6f0..c4a80ce3124c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -69,6 +69,12 @@ cpu0: cpu@0 { clock-frequency =3D <2000000000>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -81,6 +87,12 @@ cpu1: cpu@100 { clock-frequency =3D <2000000000>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -93,6 +105,12 @@ cpu2: cpu@200 { clock-frequency =3D <2000000000>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -105,6 +123,12 @@ cpu3: cpu@300 { clock-frequency =3D <2000000000>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -117,6 +141,12 @@ cpu4: cpu@400 { clock-frequency =3D <2000000000>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -129,6 +159,12 @@ cpu5: cpu@500 { clock-frequency =3D <2000000000>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; }; @@ -141,6 +177,12 @@ cpu6: cpu@600 { clock-frequency =3D <2050000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; @@ -153,6 +195,12 @@ cpu7: cpu@700 { clock-frequency =3D <2050000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; }; @@ -200,18 +248,28 @@ cluster_off_b: cluster-off-b { l2_0: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; next-level-cache =3D <&l3_0>; }; =20 l2_1: l2-cache1 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <262144>; + cache-line-size =3D <64>; + cache-sets =3D <512>; next-level-cache =3D <&l3_0>; }; =20 l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-unified; }; }; =20 --=20 2.38.1 From nobody Sat Sep 21 07:31:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0D0FC4708E for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1670325819; bh=48tAHSkcotWDq/1mQynydodHHleYUjhYYLh9z9vaE/E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VaH+ZWmLuTxCHfUaiGpfXsx9FVHf6bZKLYW4CxEs8l8GL8ZZcYJn/A3nHVgfdQ7Dh vtjQWKDIdwcsVa+XnxXZcmaTRx6Y7YPcDPwBBP207xHNC+4ko0ZXClaHM+b9TbbF1+ K6FyIoLCGy/l1VZsL720JVFt3MWYuCV7oGdw+7+t/2bE6RRnJJ3L50QBuUV8ivMbhM vHdrU3I3tIFU0oGXhftzsaIatOaURlEmPkSwwep+XZyO4yVl6cfbVzEfCU0urUSBiJ CdgqhBkTTgBc1JTDs0k3QdjFfmVQF2x5V6BRCome2efPoeRKFh5reHEhYnhw2Yb28/ 3wxepD4OolmEA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, nfraprado@collabora.com, kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 4/5] arm64: dts: mt8183: Add complete CPU caches information Date: Tue, 6 Dec 2022 12:23:29 +0100 Message-Id: <20221206112330.78431-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> References: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This SoC features two clusters composed of: - 4x Cortex A53: 32KB I-cache, 2-way set associative, 32KB D-cache, 4-way set associative, unified 1MB L2 cache, 16-way set associative; - 4x Cortex A73: 64KB I-cache and 64KB D-cache, 4-way set associative, unified 1MB L2 cache, 16-way set associative; With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index a70b669c49ba..12f61cd20da5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -336,6 +336,13 @@ cpu0: cpu@0 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; dynamic-power-coefficient =3D <84>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -352,6 +359,13 @@ cpu1: cpu@1 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; dynamic-power-coefficient =3D <84>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -368,6 +382,13 @@ cpu2: cpu@2 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; dynamic-power-coefficient =3D <84>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -384,6 +405,13 @@ cpu3: cpu@3 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; dynamic-power-coefficient =3D <84>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -400,6 +428,13 @@ cpu4: cpu@100 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster1_opp>; dynamic-power-coefficient =3D <211>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -416,6 +451,13 @@ cpu5: cpu@101 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster1_opp>; dynamic-power-coefficient =3D <211>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -432,6 +474,13 @@ cpu6: cpu@102 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster1_opp>; dynamic-power-coefficient =3D <211>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -448,6 +497,13 @@ cpu7: cpu@103 { clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster1_opp>; dynamic-power-coefficient =3D <211>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; mediatek,cci =3D <&cci>; }; @@ -481,6 +537,24 @@ CLUSTER_SLEEP1: cluster-sleep-1 { min-residency-us =3D <1300>; }; }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-unified; + }; }; =20 gpu_opp_table: opp-table-0 { --=20 2.38.1 From nobody Sat Sep 21 07:31:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF563C63704 for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1670325819; bh=h6nkSvmYgmO1NUiTtUIOSdVJ5+xRcYgOqZpZRIpVBIY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QsJHfqCoL4aa4oNImrCnUmK/JLhYSrigl9mN+TT4L5JgUPQHpzlP2EgvbQYxsqzbJ TOC+zgn4HqCJqttQYbJ11zYuh7KsmmPy7R/Mu3pQDuyDPo21XWyKIDZ13MntoIRR19 R/Ex9pmZiOFE2hvmAuepWR4p95uCLbiIRuY6tjGc1mTL/0QtvZUXtrzy0Yvd1mdIK4 gqJOsZabX5lOj5LeWfrc/+dqNN3N/kJnUBXIlzCkUEEOTijQZCKJjgA/PRbW3n/Lm0 I/LXCul8tlaR1WObeBXbgonK0iS8Zl+YJUEIHyOjmeQA9Hz4ilVUhu0PekNfp45mu1 vgNnjLd7cA4bQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, nfraprado@collabora.com, kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 5/5] arm64: dts: mt6795: Add complete CPU caches information Date: Tue, 6 Dec 2022 12:23:30 +0100 Message-Id: <20221206112330.78431-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> References: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically, four CPUs per cluster, with two CPU clusters. Each CPU has: - A 32KB I-cache, 2-way set associative; - A 32KB D-cache, 4-way set associative. Each cluster has a unified 1MB L2 cache, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts= /mediatek/mt6795.dtsi index bb575837e4ce..b3fc76d837a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -40,6 +40,12 @@ cpu1: cpu@1 { enable-method =3D "psci"; reg =3D <0x001>; cci-control-port =3D <&cci_control2>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; }; =20 @@ -49,6 +55,12 @@ cpu2: cpu@2 { enable-method =3D "psci"; reg =3D <0x002>; cci-control-port =3D <&cci_control2>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; }; =20 @@ -58,6 +70,12 @@ cpu3: cpu@3 { enable-method =3D "psci"; reg =3D <0x003>; cci-control-port =3D <&cci_control2>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; }; =20 @@ -67,6 +85,12 @@ cpu4: cpu@100 { enable-method =3D "psci"; reg =3D <0x100>; cci-control-port =3D <&cci_control1>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_1>; }; =20 @@ -76,6 +100,12 @@ cpu5: cpu@101 { enable-method =3D "psci"; reg =3D <0x101>; cci-control-port =3D <&cci_control1>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_1>; }; =20 @@ -85,6 +115,12 @@ cpu6: cpu@102 { enable-method =3D "psci"; reg =3D <0x102>; cci-control-port =3D <&cci_control1>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_1>; }; =20 @@ -94,6 +130,12 @@ cpu7: cpu@103 { enable-method =3D "psci"; reg =3D <0x103>; cci-control-port =3D <&cci_control1>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; next-level-cache =3D <&l2_1>; }; =20 @@ -138,11 +180,19 @@ core3 { l2_0: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-unified; }; =20 l2_1: l2-cache1 { compatible =3D "cache"; cache-level =3D <2>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-unified; }; }; =20 --=20 2.38.1