From nobody Thu Sep 18 13:07:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FCCEC352A1 for ; Tue, 6 Dec 2022 08:30:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234093AbiLFIa2 (ORCPT ); Tue, 6 Dec 2022 03:30:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233585AbiLFIaO (ORCPT ); Tue, 6 Dec 2022 03:30:14 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18A821B784; Tue, 6 Dec 2022 00:30:09 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso17389058pjt.0; Tue, 06 Dec 2022 00:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a04oUGY9n3fJGrXo8icImVtwc+ewjypnXhaaNSDY1GQ=; b=ffnkQM8md00BOrMgIrR3OQZYzhrii36HasWPdUxYB3CgDo6No5kJFd/i9K+xbHtLM7 1NDNH+BlJfyHXiizyks0KVClq5KwqE/ZU4E9jO5j5VNnKAsExCuivoQikD59srPvvNEq nZSVM3GZrE3aWExVe9ZFPT/p1R8nZzTgKed/QJrrQri63Xwl2vmVjv4sncRIQnvhmDbl zifnMl7Td5TfcouQlYF7i5DihELWQgL+vPGnXir/P1GWFS104Y/kvgf89Us3U6tu6UYt xkmP/zSaqQ4EeqCKiH83kcTc2DcQEe2uUSOzlOmceZnq42awAbh0Y5YV6amwVLzNiCIv LKnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a04oUGY9n3fJGrXo8icImVtwc+ewjypnXhaaNSDY1GQ=; b=hjnCny9cCulD8YGNqM4jQi18pUBqe608JPzT9VYpzij+rNhQYDAb4fF8lBpTmoaLpb JMV6JVVNgYGMD3dc5KAJ1G9JV6WtWSbBQmvZFJp9qprlPws/I13Khnabo9PQKr6/XETF ep4BwiqrPkQUiQ5yc+awZSLdXJHVNBHnCrPJLx1pxfOY7+8kdeHcs3cA0iq3PRsr129i bBdaBAa7A3DFWyqqB9a0bx0Rjdt1Ho+AiUJkWgpNZ294SDpIRZc9YxzDjKIRFwoPTN0x xxxf7/FiZfZTDdh/4zM3ygfyWMg6vn9Hs7ShRJRtHCsTT800dKhtyUfHmFYb3HVLDLy8 dBbQ== X-Gm-Message-State: ANoB5plXGkg4aTCKNpOmGAZ6GtahoGLkZr/jxWJYygprXBdE8mx72uHR 56DBIB+ya8Gj05ihDQ7JAajKz+wkSdgbEA== X-Google-Smtp-Source: AA0mqf7DfNx2wCWwDvGDShzXe33Twfhp5f1Ny7zoaA1Pz7YwoM/INQKj1y6WHGMPY802E0NoqYa0gg== X-Received: by 2002:a17:90a:9f46:b0:219:b1db:f7e3 with SMTP id q6-20020a17090a9f4600b00219b1dbf7e3mr14235394pjv.64.1670315408566; Tue, 06 Dec 2022 00:30:08 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h15-20020a056a00000f00b00574d38f4d37sm11203330pfk.45.2022.12.06.00.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 00:30:08 -0800 (PST) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini Cc: Sean Christopherson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH RESEND v3 1/3] KVM: x86/pmu: Disable guest PEBS on hybird cpu due to heterogeneity Date: Tue, 6 Dec 2022 16:29:42 +0800 Message-Id: <20221206082944.59837-2-likexu@tencent.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206082944.59837-1-likexu@tencent.com> References: <20221206082944.59837-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu From vPMU enabling perspective, KVM does not have proper support for hybird x86 core. The reported perf_capabilities value (e.g. the format of pebs record) depends on the type of cpu the kvm-intel module is init. When a vcpu of one pebs format migrates to a vcpu of another pebs format, the incorrect parsing of pebs records by guest can make profiling data analysis extremely problematic. The safe way to fix this is to disable this part of the support until the guest recognizes that it is running on the hybird cpu, which is appropriate at the moment given that x86 hybrid architectures are not heavily touted in the data center market. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/capabilities.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index cd2ac9536c99..ea0498684048 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -392,7 +392,9 @@ static inline bool vmx_pt_mode_is_host_guest(void) =20 static inline bool vmx_pebs_supported(void) { - return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept; + return boot_cpu_has(X86_FEATURE_PEBS) && + !boot_cpu_has(X86_FEATURE_HYBRID_CPU) && + kvm_pmu_cap.pebs_ept; } =20 static inline bool cpu_has_notify_vmexit(void) --=20 2.38.1 From nobody Thu Sep 18 13:07:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8B12C3A5A7 for ; Tue, 6 Dec 2022 08:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234128AbiLFIab (ORCPT ); Tue, 6 Dec 2022 03:30:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234041AbiLFIaP (ORCPT ); Tue, 6 Dec 2022 03:30:15 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3DF91A83C; Tue, 6 Dec 2022 00:30:10 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso17389135pjt.0; Tue, 06 Dec 2022 00:30:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VUAXslo7pyeEryWuDg5bgr4Jvxx+orS9YH75NmcZQEs=; b=d9gty1PChBUuJEj+eBI3FfgvQkY/AEPxGhAqOzRelh9DWWpeiNyKOQoyMrjNTQbENg D7IIni1tBrVAlJv8gav6jEZYSV40Rfz23lPb2elRxh9LY9TyCBzrWyTJDUNJRNA6HFy+ 4+dGwgLZkqQAtDoiWXHo5axbfcfgSmhyDR6/8gDYR40D+PAZ3R3YnFES5YKuPtKmdfY9 bxPW3RRSKsP1DffOEf318vatdHO//qk+38qyn1XdhmeO9cYdZtBSxkFdXIPt3SlPQg8k zGnovL94zB15A4Ic+iNIKp7YhewgE3MG6TJFFW9/7tbrts3J59jVr0QSsnWwVXg1pf0p n58g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VUAXslo7pyeEryWuDg5bgr4Jvxx+orS9YH75NmcZQEs=; b=s4eFB4lgAcVU1oZY47vWQCIMLxsGNWm45WzzwxD1EKXgKorQLnK1ss1Wdn2NkDlrsG ZwtgxfUnolz9O3zYyILDIYm2XGMBbO0rdgVFQEfZm7WfNKpQk3dSSxGzpvZQzdGWxqOL 0lSjxjo37TJp36duyEXc6dm4hIWfnMKyMdiTfcPuYdzhsCPqUCn2KLpSdwXoFVhe3OMy yWYfio4xvuMcYjXHPDFZG9cjKuwrPtFOfyy9pJWM2Q1uSZzvYkXVeiiE4nCCtuatvcIn rklzTj0yNUkAY2vUpVXH05k4HKC5JCFUlEJbmSP/kEieIpG9ES3OZY9K4vETfJkp/c5b TdPQ== X-Gm-Message-State: ANoB5pnGWz65pOy1YCRQ8YLLSeY9BqrvUWrAA7kHN8ZErMBSsIBZS2yV q2Lm+E0SANe+/y4ujWxT4oE= X-Google-Smtp-Source: AA0mqf4pU1vWZ4AaaCtpGWH7abBR/qX0KLP2JMdjCYlqSZcD1kjAJNQ0KjjJsjihSPENwTlQRUqmBg== X-Received: by 2002:a17:90a:6bc7:b0:219:ed2d:5595 with SMTP id w65-20020a17090a6bc700b00219ed2d5595mr5055021pjj.238.1670315410287; Tue, 06 Dec 2022 00:30:10 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h15-20020a056a00000f00b00574d38f4d37sm11203330pfk.45.2022.12.06.00.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 00:30:10 -0800 (PST) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini Cc: Sean Christopherson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH RESEND v3 2/3] KVM: x86/pmu: Add PRIR++ and PDist support for SPR and later models Date: Tue, 6 Dec 2022 16:29:43 +0800 Message-Id: <20221206082944.59837-3-likexu@tencent.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206082944.59837-1-likexu@tencent.com> References: <20221206082944.59837-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu The pebs capability on the SPR is basically the same as Ice Lake Server with the exception of two special facilities that have been enhanced and require special handling. Upon triggering a PEBS assist, there will be a finite delay between the time the counter overflows and when the microcode starts to carry out its data collection obligations. Even if the delay is constant in core clock space, it invariably manifest as variable "skids" in instruction address space. On the Ice Lake Server, the Precise Distribution of Instructions Retire (PDIR) facility mitigates the "skid" problem by providing an early indication of when the counter is about to overflow. On SPR, the PDIR counter available (Fixed 0) is unchanged, but the capability is enhanced to Instruction-Accurate PDIR (PDIR++), where PEBS is taken on the next instruction after the one that caused the overflow. SPR also introduces a new Precise Distribution (PDist) facility only on general programmable counter 0. Per Intel SDM, PDist eliminates any skid or shadowing effects from PEBS. With PDist, the PEBS record will be generated precisely upon completion of the instruction or operation that causes the counter to overflow (there is no "wait for next occurrence" by default). In terms of KVM handling, when guest accesses those special counters, the KVM needs to request the same index counters via the perf_event kernel subsystem to ensure that the guest uses the correct pebs hardware counter (PRIR++ or PDist). This is mainly achieved by adjusting the event precise level to the maximum, where the semantics of this magic number is mainly defined by the internal software context of perf_event and it's also backwards compatible as part of the user space interface. Opportunistically, refine confusing comments on TNT+, as the only ones that currently support pebs_ept are Ice Lake server and SPR (GLC+). Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 45 +++++++++++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 684393c22105..8c8bfd078a3f 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -28,9 +28,18 @@ struct x86_pmu_capability __read_mostly kvm_pmu_cap; EXPORT_SYMBOL_GPL(kvm_pmu_cap); =20 -static const struct x86_cpu_id vmx_icl_pebs_cpu[] =3D { +/* Precise Distribution of Instructions Retired (PDIR) */ +static const struct x86_cpu_id vmx_pebs_pdir_cpu[] =3D { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL), + /* Instruction-Accurate PDIR (PDIR++) */ + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), + {} +}; + +/* Precise Distribution (PDist) */ +static const struct x86_cpu_id vmx_pebs_pdist_cpu[] =3D { + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), {} }; =20 @@ -155,6 +164,28 @@ static void kvm_perf_overflow(struct perf_event *perf_= event, kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } =20 +static u64 pmc_get_pebs_precise_level(struct kvm_pmc *pmc) +{ + /* + * For some model specific pebs counters with special capabilities + * (PDIR, PDIR++, PDIST), KVM needs to raise the event precise + * level to the maximum value (currently 3, backwards compatible) + * so that the perf subsystem would assign specific hardware counter + * with that capability for vPMC. + */ + if ((pmc->idx =3D=3D 0 && x86_match_cpu(vmx_pebs_pdist_cpu)) || + (pmc->idx =3D=3D 32 && x86_match_cpu(vmx_pebs_pdir_cpu))) + return 3; + + /* + * The non-zero precision level of guest event makes the ordinary + * guest event becomes a guest PEBS event and triggers the host + * PEBS PMI handler to determine whether the PEBS overflow PMI + * comes from the host counters or the guest. + */ + return 1; +} + static int pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config, bool exclude_user, bool exclude_kernel, bool intr) @@ -186,22 +217,12 @@ static int pmc_reprogram_counter(struct kvm_pmc *pmc,= u32 type, u64 config, } if (pebs) { /* - * The non-zero precision level of guest event makes the ordinary - * guest event becomes a guest PEBS event and triggers the host - * PEBS PMI handler to determine whether the PEBS overflow PMI - * comes from the host counters or the guest. - * * For most PEBS hardware events, the difference in the software * precision levels of guest and host PEBS events will not affect * the accuracy of the PEBS profiling result, because the "event IP" * in the PEBS record is calibrated on the guest side. - * - * On Icelake everything is fine. Other hardware (GLC+, TNT+) that - * could possibly care here is unsupported and needs changes. */ - attr.precise_ip =3D 1; - if (x86_match_cpu(vmx_icl_pebs_cpu) && pmc->idx =3D=3D 32) - attr.precise_ip =3D 3; + attr.precise_ip =3D pmc_get_pebs_precise_level(pmc); } =20 event =3D perf_event_create_kernel_counter(&attr, -1, current, --=20 2.38.1 From nobody Thu Sep 18 13:07:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 052B8C3A5A7 for ; Tue, 6 Dec 2022 08:30:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231779AbiLFIag (ORCPT ); Tue, 6 Dec 2022 03:30:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233928AbiLFIaP (ORCPT ); Tue, 6 Dec 2022 03:30:15 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AAE51AD97; Tue, 6 Dec 2022 00:30:13 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id b13-20020a17090a5a0d00b0021906102d05so14075761pjd.5; Tue, 06 Dec 2022 00:30:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x4H9uEd2CTHNwSO9zkkhB6GGsRkjPW9q6aNFznzOIuA=; b=eqXU0JrlUMmKM/33ndMGd7IBaBh2rYY1aFwhSs4o2njfDwpmTiUEQ5qiv8z5icJ+9n VNM5IaLFLG16GTmtxYeYecs/Pc5+Z+OHU173oCl2VaYDlEyhVAhhJQmqm4ZWV5vqQd+o lmIXdoRYO8v3J+HwnGsaXuA5kuADrEx97ogBkQcopnqQIZTqg8RjOFL6STJO6GpxExHR 0dxwOaVeHtVSNhZqCQs9UO6r9WzV5ySA9D4c2PE2z16E03yWfXcXvLxh+K8A4OvCR7UJ +Kf2I6vfhKb90HEF1IGyDpFOsOKYrE7O6h1zreV/4Hc5KkrCzDPWVu/lcr4+UvGJPDqe us2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x4H9uEd2CTHNwSO9zkkhB6GGsRkjPW9q6aNFznzOIuA=; b=1BhwCg14xlHJulzGlqnR2s7OdctL/Jme7rg8Qx0XaSkvoQrRgrynMpQlS+wK+zpyMr dGfHdcQMAseDYwj0+UA5AFBScLDhuVZ2LWMxn99IgSQoI5XizxoyR35voPv6/gEskTw6 0512+yRp6mcZYMu7lDp63hmdjt5Rt/+5u4raecNL/8YmsSbFFmw26zShMMXv3swM/XMo cghKdCozl0wTwTostNZZlBaDk0ZX6vRK3FWFQU2e/TlXvN7Ov/IbxpR3Gsjc+QcPxBJt +2n7ns6AFAGFpqOx3L6rK9Dl5PvgN/+Lre9Jz3wMYDwsWCGmgSNJdvE4yl8Vr5ltpG6/ rLqw== X-Gm-Message-State: ANoB5pnKaaV50UEoWqLtPaTY0PLztrtRnmAoDDCm8+5QMnnq7b1hmf+D 7Og389BTn3EwdFASo1oqg5EMkVWA3J4ejg== X-Google-Smtp-Source: AA0mqf4i9nNQHsxtunW4a6J3718BD8rfqPS2sYMY6QgGEbPHrv3j0GhcZjGlJdiD6KfpjFlUPFTXCw== X-Received: by 2002:a17:90b:3941:b0:215:db2e:bb17 with SMTP id oe1-20020a17090b394100b00215db2ebb17mr93396774pjb.166.1670315412841; Tue, 06 Dec 2022 00:30:12 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h15-20020a056a00000f00b00574d38f4d37sm11203330pfk.45.2022.12.06.00.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 00:30:12 -0800 (PST) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini Cc: Sean Christopherson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Peter Zijlstra , linux-perf-users@vger.kernel.org, Kan Liang Subject: [PATCH RESEND v3 3/3] perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models Date: Tue, 6 Dec 2022 16:29:44 +0800 Message-Id: <20221206082944.59837-4-likexu@tencent.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206082944.59837-1-likexu@tencent.com> References: <20221206082944.59837-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu According to Intel SDM, the EPT-friendly PEBS is supported by all the platforms after ICX, ADL and the future platforms with PEBS format 5. Currently the only in-kernel user of this capability is KVM, which has very limited support for hybrid core pmu, so ADL and its successors do not currently expose this capability. When both hybrid core and PEBS format 5 are present, KVM will decide on its own merits. Cc: Peter Zijlstra Cc: linux-perf-users@vger.kernel.org Suggested-by: Kan Liang Signed-off-by: Like Xu Reviewed-by: Kan Liang Acked-by: Peter Zijlstra (Intel) --- Nit: This change is proposed to be applied via the KVM tree. arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 1b92bf05fd65..e7e31b9d24d3 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6351,6 +6351,7 @@ __init int intel_pmu_init(void) x86_pmu.pebs_constraints =3D intel_spr_pebs_event_constraints; x86_pmu.extra_regs =3D intel_spr_extra_regs; x86_pmu.limit_period =3D spr_limit_period; + x86_pmu.pebs_ept =3D 1; x86_pmu.pebs_aliases =3D NULL; x86_pmu.pebs_prec_dist =3D true; x86_pmu.pebs_block =3D true; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 446d2833efa7..7258dca6882f 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2303,8 +2303,10 @@ void __init intel_ds_init(void) x86_pmu.large_pebs_flags |=3D PERF_SAMPLE_TIME; break; =20 - case 4: case 5: + x86_pmu.pebs_ept =3D 1; + fallthrough; + case 4: x86_pmu.drain_pebs =3D intel_pmu_drain_pebs_icl; x86_pmu.pebs_record_size =3D sizeof(struct pebs_basic); if (x86_pmu.intel_cap.pebs_baseline) { --=20 2.38.1