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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E658.mail.protection.outlook.com (10.167.18.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.8 via Frontend Transport; Tue, 6 Dec 2022 04:33:30 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 22:33:24 -0600 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/2] perf test: Add event group test Date: Tue, 6 Dec 2022 10:02:37 +0530 Message-ID: <20221206043237.12159-3-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221206043237.12159-1-ravi.bangoria@amd.com> References: <20221206043237.12159-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E658:EE_|PH8PR12MB6697:EE_ X-MS-Office365-Filtering-Correlation-Id: a8714af8-6a23-4ab3-dcc0-08dad74306dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 04:33:30.3483 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8714af8-6a23-4ab3-dcc0-08dad74306dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E658.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6697 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Multiple events in a group can belong to one or more pmus, however there are some limitations to it. One of the limitation is, perf doesn't allow creating a group of events from different hw pmus. Write a simple test to create various combinations of hw, sw and uncore pmu events and verify group creation succeeds or fails as expected. Signed-off-by: Ravi Bangoria Acked-by: Madhavan Srinivasan --- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test.c | 1 + tools/perf/tests/event_groups.c | 127 ++++++++++++++++++++++++++++++++ tools/perf/tests/tests.h | 1 + 4 files changed, 130 insertions(+) create mode 100644 tools/perf/tests/event_groups.c diff --git a/tools/perf/tests/Build b/tools/perf/tests/Build index 11b69023011b..658b5052c24d 100644 --- a/tools/perf/tests/Build +++ b/tools/perf/tests/Build @@ -67,6 +67,7 @@ perf-y +=3D expand-cgroup.o perf-y +=3D perf-time-to-tsc.o perf-y +=3D dlfilter-test.o perf-y +=3D sigtrap.o +perf-y +=3D event_groups.o =20 $(OUTPUT)tests/llvm-src-base.c: tests/bpf-script-example.c tests/Build $(call rule_mkdir) diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-tes= t.c index 4c6ae59a4dfd..ddd8262bfa26 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -110,6 +110,7 @@ static struct test_suite *generic_tests[] =3D { &suite__perf_time_to_tsc, &suite__dlfilter, &suite__sigtrap, + &suite__event_groups, NULL, }; =20 diff --git a/tools/perf/tests/event_groups.c b/tools/perf/tests/event_group= s.c new file mode 100644 index 000000000000..612c0444aaa8 --- /dev/null +++ b/tools/perf/tests/event_groups.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include "linux/perf_event.h" +#include "tests.h" +#include "debug.h" +#include "pmu.h" +#include "pmus.h" +#include "header.h" +#include "../perf-sys.h" + +/* hw: cycles, sw: context-switch, uncore: [arch dependent] */ +static int types[] =3D {0, 1, -1}; +static unsigned long configs[] =3D {0, 3, 0}; + +#define NR_UNCORE_PMUS 5 + +/* Uncore pmus that support more than 3 counters */ +static struct uncore_pmus { + const char *name; + __u64 config; +} uncore_pmus[NR_UNCORE_PMUS] =3D { + { "amd_l3", 0x0 }, + { "amd_df", 0x0 }, + { "uncore_imc_0", 0x1 }, /* Intel */ + { "core_imc", 0x318 }, /* PowerPC: core_imc/CPM_STCX_FIN/ */ + { "hv_24x7", 0x22000000003 }, /* PowerPC: hv_24x7/CPM_STCX_FIN/ */ +}; + +static int event_open(int type, unsigned long config, int group_fd) +{ + struct perf_event_attr attr; + + memset(&attr, 0, sizeof(struct perf_event_attr)); + attr.type =3D type; + attr.size =3D sizeof(struct perf_event_attr); + attr.config =3D config; + /* + * When creating an event group, typically the group leader is + * initialized with disabled set to 1 and any child events are + * initialized with disabled set to 0. Despite disabled being 0, + * the child events will not start until the group leader is + * enabled. + */ + attr.disabled =3D group_fd =3D=3D -1 ? 1 : 0; + + return sys_perf_event_open(&attr, -1, 0, group_fd, 0); +} + +static int setup_uncore_event(void) +{ + struct perf_pmu *pmu; + int i; + + if (list_empty(&pmus)) + perf_pmu__scan(NULL); + + perf_pmus__for_each_pmu(pmu) { + for (i =3D 0; i < NR_UNCORE_PMUS; i++) { + if (!strcmp(uncore_pmus[i].name, pmu->name)) { + pr_debug("Using %s for uncore pmu event\n", pmu->name); + types[2] =3D pmu->type; + configs[2] =3D uncore_pmus[i].config; + return 0; + } + } + } + return -1; +} + +static int run_test(int i, int j, int k) +{ + int erroneous =3D ((((1 << i) | (1 << j) | (1 << k)) & 5) =3D=3D 5); + int group_fd, sibling_fd1, sibling_fd2; + + group_fd =3D event_open(types[i], configs[i], -1); + if (group_fd =3D=3D -1) + return -1; + + sibling_fd1 =3D event_open(types[j], configs[j], group_fd); + if (sibling_fd1 =3D=3D -1) { + close(group_fd); + return erroneous ? 0 : -1; + } + + sibling_fd2 =3D event_open(types[k], configs[k], group_fd); + if (sibling_fd2 =3D=3D -1) { + close(sibling_fd1); + close(group_fd); + return erroneous ? 0 : -1; + } + + close(sibling_fd2); + close(sibling_fd1); + close(group_fd); + return erroneous ? -1 : 0; +} + +static int test__event_groups(struct test_suite *text __maybe_unused, int = subtest __maybe_unused) +{ + int i, j, k; + int ret; + int r; + + ret =3D setup_uncore_event(); + if (ret || types[2] =3D=3D -1) + return TEST_SKIP; + + ret =3D TEST_OK; + for (i =3D 0; i < 3; i++) { + for (j =3D 0; j < 3; j++) { + for (k =3D 0; k < 3; k++) { + r =3D run_test(i, j, k); + if (r) + ret =3D TEST_FAIL; + + pr_debug("0x%x 0x%lx, 0x%x 0x%lx, 0x%x 0x%lx: %s\n", + types[i], configs[i], types[j], configs[j], + types[k], configs[k], r ? "Fail" : "Pass"); + } + } + } + return ret; +} + +DEFINE_SUITE("Event groups", event_groups); diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h index e15f24cfc909..fb4b5ad4dd0f 100644 --- a/tools/perf/tests/tests.h +++ b/tools/perf/tests/tests.h @@ -147,6 +147,7 @@ DECLARE_SUITE(expand_cgroup_events); DECLARE_SUITE(perf_time_to_tsc); DECLARE_SUITE(dlfilter); DECLARE_SUITE(sigtrap); +DECLARE_SUITE(event_groups); =20 /* * PowerPC and S390 do not support creation of instruction breakpoints usi= ng the --=20 2.38.1