From nobody Thu Sep 18 15:58:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C261AC4708D for ; Mon, 5 Dec 2022 17:47:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230123AbiLERri (ORCPT ); Mon, 5 Dec 2022 12:47:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232358AbiLERrI (ORCPT ); Mon, 5 Dec 2022 12:47:08 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99B94233AB; Mon, 5 Dec 2022 09:45:48 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1330E61280; Mon, 5 Dec 2022 17:45:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 972B2C43470; Mon, 5 Dec 2022 17:45:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1670262347; bh=FmsPC9vkAuOSeyIidXhZGduvRa/XcRXnLCs2H58uKvc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CvoenScK84bXEcVw22KBdxXQ0dTV86dyI/T/dik2Uj0QKklr1vDO9BpdvI6AtqdF2 vzEB8kgauiVefFjhIUsA4+isEo6xVUHh5L0ilFJXOrzMDxSxBQqYXj9jznQnlKb+di FuD0Fz8YK4GiLcCsAK4P4rBlb1whgliGRP0dLBLPeIIA4Jtk4QyYcIw+0wjyVdJEdh oNhFSdIwLZbJI9XnjjvcVIBxZf625OlwJr26PHBO7i1sT3dqE21uPfJLlGE+GRwgn1 5GoWg1fabLz1FLSE3y9BbLq0eJpEdL8YLhejMymzSXCExMQxbRnkG/F6gNXWYL4nEy shwi9zBkE1z1w== From: Conor Dooley To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Conor Dooley , Jessica Clarke , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Heiko Stuebner , Andrew Jones , Guo Ren , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt Subject: [PATCH v3 2/2] dt-bindings: riscv: fix single letter canonical order Date: Mon, 5 Dec 2022 17:45:00 +0000 Message-Id: <20221205174459.60195-3-conor@kernel.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221205174459.60195-1-conor@kernel.org> References: <20221205174459.60195-1-conor@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley I used the wikipedia table for ordering extensions when updating the pattern here in commit 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators"). Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-p= df-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emu= lators") Acked-by: Guo Ren Reviewed-by: Heiko Stuebner Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 97659bb71811..d4148418350c 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz= ](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[= hsxz](?:[a-z])+)*$ =20 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false --=20 2.38.1