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[95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:00 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Cc: Rob Herring Subject: [PATCH v3 01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Date: Mon, 5 Dec 2022 17:37:44 +0100 Message-Id: <20221205163754.221139-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm83= 50-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml new file mode 100644 index 000000000000..120500395c9a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display DPU + +maintainers: + - Robert Foss + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible =3D "qcom,sm8350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz =3D /bits/ 64 <345000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; +... --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2438C4332F for ; Mon, 5 Dec 2022 16:39:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233112AbiLEQjx (ORCPT ); Mon, 5 Dec 2022 11:39:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232739AbiLEQjR (ORCPT ); Mon, 5 Dec 2022 11:39:17 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F57920186 for ; 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[95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:02 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding Date: Mon, 5 Dec 2022 17:37:45 +0100 Message-Id: <20221205163754.221139-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for MDSS device tree bindings Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- .../display/msm/qcom,sm8350-mdss.yaml | 221 ++++++++++++++++++ 1 file changed, 221 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm83= 50-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml new file mode 100644 index 000000000000..d9aa6e857d1f --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display MDSS + +maintainers: + - Robert Foss + +description: + MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: mdp0-mem + - const: mdp1-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-5nm-8350 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm8350-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + power-domains =3D <&dispcc MDSS_GDSC>; + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + iommus =3D <&apps_smmu 0x820 0x402>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm8350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz =3D /bits/ 64 <345000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, + <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + phys =3D <&dsi0_phy>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +... --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB7FEC4332F for ; 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[95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:03 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog Date: Mon, 5 Dec 2022 17:37:46 +0100 Message-Id: <20221205163754.221139-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatibility for SM8350 display subsystem, including required entries in DPU hw catalog. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + 2 files changed, 197 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 4dac90ee5b8a..ba26af73be53 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -112,6 +112,15 @@ BIT(MDP_INTF3_INTR) | \ BIT(MDP_INTF4_INTR)) =20 +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR) | \ + 0) + #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ BIT(MDP_SSPP_TOP0_INTR2) | \ BIT(MDP_SSPP_TOP0_HIST_INTR) | \ @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps =3D { .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, }; =20 +static const struct dpu_caps sm8350_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .qseed_type =3D DPU_SSPP_SCALER_QSEED3LITE, + .smart_dma_rev =3D DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .ubwc_version =3D DPU_HW_UBWC_VER_40, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 4096, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + static const struct dpu_caps sm8450_dpu_caps =3D { .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] =3D { }, }; =20 +static const struct dpu_mdp_cfg sm8350_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .highest_bank_bit =3D 0x3, /* TODO: 2 for LP_DDR4 */ + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { + .reg_off =3D 0x2ac, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] =3D { + .reg_off =3D 0x2b4, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] =3D { + .reg_off =3D 0x2bc, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] =3D { + .reg_off =3D 0x2c4, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { + .reg_off =3D 0x2ac, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] =3D { + .reg_off =3D 0x2b4, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] =3D { + .reg_off =3D 0x2bc, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] =3D { + .reg_off =3D 0x2c4, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] =3D { + .reg_off =3D 0x2bc, .bit_off =3D 20}, + }, +}; + static const struct dpu_mdp_cfg sm8450_mdp[] =3D { { .name =3D "top_0", .id =3D MDP_TOP, @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] =3D { }, }; =20 +static const struct dpu_ctl_cfg sm8350_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1e8, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1e8, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + static const struct dpu_ctl_cfg sm8450_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, @@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] =3D= { -1), }; =20 +static const struct dpu_pingpong_cfg sm8350_pp[] =3D { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_t= e, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_t= e, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), +}; + static struct dpu_pingpong_cfg qcm2290_pp[] =3D { PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), @@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d= [] =3D { MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), }; =20 +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] =3D { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), +}; + static const struct dpu_merge_3d_cfg sm8450_merge_3d[] =3D { MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), @@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] =3D { DSC_BLK("dsc_3", DSC_3, 0x80c00), }; =20 +static struct dpu_dsc_cfg sm8350_dsc[] =3D { + DSC_BLK("dsc_0", DSC_0, 0x80000), + DSC_BLK("dsc_1", DSC_1, 0x81000), + DSC_BLK("dsc_2", DSC_2, 0x82000), +}; + /************************************************************* * INTF sub blocks config *************************************************************/ @@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), }; =20 +static const struct dpu_intf_cfg sm8350_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MD= P_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MD= P_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + static const struct dpu_intf_cfg sc8180x_intf[] =3D { INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INT= F_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MD= P_SSPP_TOP0_INTR, 26, 27), @@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = =3D { .clk_ctrl =3D DPU_CLK_CTRL_REG_DMA, }; =20 +static const struct dpu_reg_dma_cfg sm8350_regdma =3D { + .base =3D 0x400, + .version =3D 0x00020000, + .trigger_sel_off =3D 0x119c, + .xin_id =3D 7, + .clk_ctrl =3D DPU_CLK_CTRL_REG_DMA, +}; + static const struct dpu_reg_dma_cfg sm8450_regdma =3D { .base =3D 0x0, .version =3D 0x00020000, @@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = =3D { .bw_inefficiency_factor =3D 120, }; =20 +static const struct dpu_perf_cfg sm8350_perf_data =3D { + .max_bw_low =3D 11800000, + .max_bw_high =3D 15500000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 40, + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + static const struct dpu_perf_cfg qcm2290_perf_data =3D { .max_bw_low =3D 2700000, .max_bw_high =3D 2700000, @@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg =3D { .mdss_irqs =3D IRQ_SM8250_MASK, }; =20 +static const struct dpu_mdss_cfg sm8350_dpu_cfg =3D { + .caps =3D &sm8350_dpu_caps, + .mdp_count =3D ARRAY_SIZE(sm8350_mdp), + .mdp =3D sm8350_mdp, + .ctl_count =3D ARRAY_SIZE(sm8350_ctl), + .ctl =3D sm8350_ctl, + .sspp_count =3D ARRAY_SIZE(sm8250_sspp), + .sspp =3D sm8250_sspp, + .mixer_count =3D ARRAY_SIZE(sm8150_lm), + .mixer =3D sm8150_lm, + .dspp_count =3D ARRAY_SIZE(sm8150_dspp), + .dspp =3D sm8150_dspp, + .pingpong_count =3D ARRAY_SIZE(sm8350_pp), + .pingpong =3D sm8350_pp, + .dsc_count =3D ARRAY_SIZE(sm8350_dsc), + .dsc =3D sm8350_dsc, + .merge_3d_count =3D ARRAY_SIZE(sm8350_merge_3d), + .merge_3d =3D sm8350_merge_3d, + .intf_count =3D ARRAY_SIZE(sm8350_intf), + .intf =3D sm8350_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .reg_dma_count =3D 1, + .dma_cfg =3D &sm8250_regdma, + .perf =3D &sm8350_perf_data, + .mdss_irqs =3D IRQ_SM8350_MASK, +}; + static const struct dpu_mdss_cfg sm8450_dpu_cfg =3D { .caps =3D &sm8450_dpu_caps, .mdp_count =3D ARRAY_SIZE(sm8450_mdp), @@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handl= er[] =3D { { .hw_rev =3D DPU_HW_VER_600, .dpu_cfg =3D &sm8250_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_620, .dpu_cfg =3D &sc7180_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_650, .dpu_cfg =3D &qcm2290_dpu_cfg}, + { .hw_rev =3D DPU_HW_VER_700, .dpu_cfg =3D &sm8350_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_720, .dpu_cfg =3D &sc7280_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_810, .dpu_cfg =3D &sm8450_dpu_cfg}, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 664c4876f44a..5335123a0289 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -45,6 +45,7 @@ #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ =20 --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07C08C4332F for ; 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[95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:05 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350 Date: Mon, 5 Dec 2022 17:37:47 +0100 Message-Id: <20221205163754.221139-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatibles string, "qcom,sm8350-dpu", for the display processing unit used on Qualcomm SM8350 platform. Signed-off-by: Robert Foss Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 9827914dc096..6048bfae0824 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-dpu", }, { .compatible =3D "qcom,sm8150-dpu", }, { .compatible =3D "qcom,sm8250-dpu", }, + { .compatible =3D "qcom,sm8350-dpu", }, { .compatible =3D "qcom,sm8450-dpu", }, {} }; --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89FEEC4332F for ; Mon, 5 Dec 2022 16:40:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233150AbiLEQkL (ORCPT ); Mon, 5 Dec 2022 11:40:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232831AbiLEQjW (ORCPT ); Mon, 5 Dec 2022 11:39:22 -0500 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD5C120373 for ; Mon, 5 Dec 2022 08:38:07 -0800 (PST) Received: by mail-ed1-x534.google.com with SMTP id m19so16541282edj.8 for ; Mon, 05 Dec 2022 08:38:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FA6VZLr8EX+1LwmM9brJgk2AqL1UbJ0XsUIaiz9n7JY=; b=tuw0NhESTq3UZ+zy40f7o9AcmkK+r5BotJvqEeJrQPDv77id5pMwvQOHANJ2pRtiTl xfu6zuqe1cvA141nvEgxDsqRM6STYF64bsrkifcmQGHQfR6upjeQ2pNje7FVJr/e3bD/ 7Q8yXuYkEQkCGpUntC88RpDTIMB7KJ7F4idNK0jBre+Ez8Wn5egIntB5VRXzSDec4ICR xn0GB/c0+JK1b0gWuCkNWcFtQ/QTSlNO8lezjo0kRY1JbCt35Vss2vzU4viHBqOU6Ciy wUKYJF+T/HFTNyQQwori8EBSxhi4ogLMiDJpL5GPTOcJnuPfL2KtbCtqReGC/cMny0BV sPKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FA6VZLr8EX+1LwmM9brJgk2AqL1UbJ0XsUIaiz9n7JY=; b=TKaO4nxDy0/n3RhFL1XgPCEW5LsPZziwpc5k5QwXrnSf2VOBmvpSgYqBOvS5VJE3ud 2l7tiRzQ3IBH0KlZxyahTrVhehjMWu6DClDzoFAquVKN79aK8orw+bSIHcQhMRZ1t8qo 8n/eRapSIsxTYRCKp6DmN75gi61Z/Z56CZGumzbenBy3xfPTUEn4zQXy+bjc2JLdL5bl SLRUpvkms5B2HXci6zwgAK4ZMHUmu/XoQC1vjfwddQsLQzicGyZNKKXPT48C0hX/ERyl vpBWVudG7pEFPECgsH4IUm+K3nm3kVcSYqt//YdNBvnsJQh5grc0tdSRQUS4uyb519HI 5I1A== X-Gm-Message-State: ANoB5plU7bnirCQJ8z4D7ANe5OyoLuqaisddVbAp0PPwyHfAGY5TvcMK FFGxqd8I/lI9eKYbHXf1FHL5rA== X-Google-Smtp-Source: AA0mqf4UTFIOaQqMzS0VIDvYTbzzH/oX2gTN+rgxrjAy0Q4o2IYeg3hUbwZ7Nzsbb/5KoI4Sh/LVdw== X-Received: by 2002:aa7:d556:0:b0:45c:6467:94e2 with SMTP id u22-20020aa7d556000000b0045c646794e2mr73784880edr.295.1670258287354; Mon, 05 Dec 2022 08:38:07 -0800 (PST) Received: from prec5560.localdomain (ip5f58f364.dynamic.kabel-deutschland.de. [95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:06 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 05/11] drm/msm: Add support for SM8350 Date: Mon, 5 Dec 2022 17:37:48 +0100 Message-Id: <20221205163754.221139-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatibles string, "qcom,sm8350-mdss", for the multimedia display subsystem unit used on Qualcomm SM8350 platform. Signed-off-by: Robert Foss Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index a2264fb517a1..39746b972cdd 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) /* UBWC_2_0 */ msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); break; + case DPU_HW_VER_700: + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); + break; case DPU_HW_VER_720: msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, + { .compatible =3D "qcom,sm8350-mdss" }, { .compatible =3D "qcom,sm8450-mdss" }, {} }; --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D15C9C636F9 for ; Mon, 5 Dec 2022 16:40:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233188AbiLEQkT (ORCPT ); Mon, 5 Dec 2022 11:40:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232947AbiLEQjZ (ORCPT ); Mon, 5 Dec 2022 11:39:25 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E0702035C for ; Mon, 5 Dec 2022 08:38:10 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id n21so29152257ejb.9 for ; Mon, 05 Dec 2022 08:38:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tH0W6Q+n5Go7kNaJjIz/J403hZWvc6cemePnkkWb/v0=; b=dZ4M1LL8Op3l+Rb8bBfN0q3fnNSQREE29DUO9Src6RwketawSB+KCCxWmTz1XoEeIM 7IkHQFGPFjOhFQQsWIH+nij37ov6ACjsk+PksuLwcZecwF3I0PI2F21jOvSP2KhYHven A8se9P304w8a4t+ahScyVp+u5BFw+zD16CNnrpt1iZQ85wEyyt+ebDGmfqDwy5zVF/5m Sx/Bk8CkBgRij32jE9azfx+0UD+GJvh8cGUpUPDyGGP0Esmhakl/67RqS1hroDNQZWIU uarwxX/J0oTWzJ0c/9CLImURo8hpkgkMT2IKwxyeiS8NJ5e0nGBhiKGKwnOSpp6mPWvw 5hxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tH0W6Q+n5Go7kNaJjIz/J403hZWvc6cemePnkkWb/v0=; b=Uqnk2jcxwEJHx92am6TNJtegE40I6itFiyJi73h1ahzr2O1ibv2f4i+gNaVxps7ib5 3fIEs1KfNJ0tEm2GGUhXHK4SGhQgYNHcIiPu6LwWV2uS1UTzFa+P6xikrSqebE1TytEK fnzbOD4um5qQiYfJHoNMMt45by4LyAZN0en4YS9OzwIpjD2Mee/hhW0llCmSlQrZ6qwQ 29Bg+nylPBWI/zQUHjgBJM1LIHLcW9TkljU+CG7MDpfoLdxd/5cYYjhGY5+dHrwGarr1 D28nPB3Y91u9TaDO1BB6tWDnN+tEirF9W3ZWYoAgNWUO8dYM2/C6KwzH5GOah4EnI7rs Am8Q== X-Gm-Message-State: ANoB5plP0B83MUD3boRBv81UWx/O6QzKHqczsiDTVJVM8keUeXXeZoik /4Fg/nBR0oAQb67He33VjOYFLQ== X-Google-Smtp-Source: AA0mqf75RDx/GQjdWXXRJAAYmDg1BAnjFPqibz4mqRABC7pDEDjOLBigXiI2VW5EKb4pvAFS4zlvvw== X-Received: by 2002:a17:906:5055:b0:78d:cdce:bc52 with SMTP id e21-20020a170906505500b0078dcdcebc52mr56413954ejk.469.1670258289023; Mon, 05 Dec 2022 08:38:09 -0800 (PST) Received: from prec5560.localdomain (ip5f58f364.dynamic.kabel-deutschland.de. [95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:08 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Date: Mon, 5 Dec 2022 17:37:49 +0100 Message-Id: <20221205163754.221139-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add GPIO line names as described by the sm8350-hdk schematic. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205 ++++++++++++++++++++++++ 1 file changed, 205 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8350-hdk.dts index 0fcf5bd88fc7..e6deb08c6da0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -233,6 +233,211 @@ &slpi { =20 &tlmm { gpio-reserved-ranges =3D <52 8>; + + gpio-line-names =3D + "APPS_I2C_SDA", /* GPIO_0 */ + "APPS_I2C_SCL", + "FSA_INT_N", + "USER_LED3_EN", + "SMBUS_SDA_1P8", + "SMBUS_SCL_1P8", + "2M2_3P3_EN", + "ALERT_DUAL_M2_N", + "EXP_UART_CTS", + "EXP_UART_RFR", + "EXP_UART_TX", /* GPIO_10 */ + "EXP_UART_RX", + "NC", + "NC", + "RCM_MARKER1", + "WSA0_EN", + "CAM1_RESET_N", + "CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP0_RESET_N", + "DISP1_RESET_N", + "ETH_RESET", + "RCM_MARKER2", + "CAM_DC_MIPI_MUX_EN", + "CAM_DC_MIPI_MUX_SEL", + "AFC_PHY_TA_D_PLUS", /* GPIO_30 */ + "AFC_PHY_TA_D_MINUS", + "PM8008_1_IRQ", + "PM8008_1_RESET_N", + "PM8008_2_IRQ", + "PM8008_2_RESET_N", + "CAM_DC_I3C_SDA", + "CAM_DC_I3C_SCL", + "FP_INT_N", + "FP_WUHB_INT_N", + "SMB_SPMI_DATA", /* GPIO_40 */ + "SMB_SPMI_CLK", + "USB_HUB_RESET", + "FORCE_USB_BOOT", + "LRF_IRQ", + "NC", + "IMU2_INT", + "HDMI_3P3_EN", + "HDMI_RSTN", + "HDMI_1P2_EN", + "HDMI_INT", /* GPIO_50 */ + "USB1_ID", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCLC", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HST_SW_CTRL", + "NC", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "CAM_DC_SPI0_MISO", + "CAM_DC_SPI0_MOSI", + "CAM_DC_SPI0_CLK", + "CAM_DC_SPI0_CS_N", + "CAM_DC_SPI1_MISO", + "CAM_DC_SPI1_MOSI", + "CAM_DC_SPI1_CLK", + "CAM_DC_SPI1_CS_N", + "HALL_INT_N", /* GPIO_80 */ + "USB_PHY_PS", + "MDP_VSYNC_P", + "MDP_VSYNC_S", + "ETH_3P3_EN", + "RADAR_INT", + "NFC_DWL_REQ", + "SM_GPIO_87", + "WCD_RESET_N", + "ALSP_INT_N", + "PRESS_INT", /* GPIO_90 */ + "SAR_INT_N", + "SD_CARD_DET_N", + "NC", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "PCIE1_RESET_N", + "PCIE1_CLK_REQ_N", + "PCIE1_WAKE_N", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CAM_MCLK4", + "CAM_MCLK5", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "CAM5_RESET_N", + "CAM4_RESET_N", + "CAM3_RESET_N", + "IMU1_INT", + "MAG_INT_N", + "MI2S2_I2S_SCK", /* GPIO_120 */ + "MI2S2_I2S_DAT0", + "MI2S2_I2S_WS", + "HIFI_DAC_I2S_MCLK", + "MI2S2_I2S_DAT1", + "HIFI_DAC_I2S_SCK", + "HIFI_DAC_I2S_DAT0", + "NC", + "HIFI_DAC_I2S_WS", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "BT_LED_EN", + "WLAN_LED_EN", + "NC", + "NC", + "NC", + "UIM2_PRESENT", + "NC", + "NC", + "NC", + "UIM1_PRESENT", /* GPIO_140 */ + "NC", + "SM_RFFE0_DATA", + "NC", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DSI0_STATUS", + "DSI1_STATUS", + "APPS_PBL_BOOT_SPEED_1", + "APPS_BOOT_FROM_ROM", + "APPS_PBL_BOOT_SPEED_0", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "DMIC01_CLK", + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "WSA_SWR_CLK", + "WSA_SWR_DATA", + "DMIC45_CLK", /* GPIO_180 */ + "DMIC45_DATA", + "WCD_SWR_TX_DATA2", + "SENSOR_I3C_SDA", + "SENSOR_I3C_SCL", + "CAM_OIS0_I3C_SDA", + "CAM_OIS0_I3C_SCL", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "RADAR_SPI_MISO", + "RADAR_SPI_MOSI", + "RADAR_SPI_CLK", + "RADAR_SPI_CS_N", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; }; =20 &uart2 { --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD2B7C4332F for ; Mon, 5 Dec 2022 16:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232783AbiLEQk0 (ORCPT ); Mon, 5 Dec 2022 11:40:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232957AbiLEQjZ (ORCPT ); Mon, 5 Dec 2022 11:39:25 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38194205C4 for ; Mon, 5 Dec 2022 08:38:11 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id x22so6822028ejs.11 for ; Mon, 05 Dec 2022 08:38:11 -0800 (PST) DKIM-Signature: v=1; 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[95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:10 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Cc: Konrad Dybcio Subject: [PATCH v3 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Date: Mon, 5 Dec 2022 17:37:50 +0100 Message-Id: <20221205163754.221139-8-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mmxc power-domain-name is not required, and is not used by either earlier or later SoC versions (sm8250 / sm8450). Signed-off-by: Robert Foss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index cbd48f248df4..805d53d91952 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2558,7 +2558,6 @@ dispcc: clock-controller@af00000 { #power-domain-cells =3D <1>; =20 power-domains =3D <&rpmhpd SM8350_MMCX>; - power-domain-names =3D "mmcx"; }; =20 adsp: remoteproc@17300000 { --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D33C4332F for ; Mon, 5 Dec 2022 16:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233233AbiLEQkc (ORCPT ); Mon, 5 Dec 2022 11:40:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232284AbiLEQjZ (ORCPT ); Mon, 5 Dec 2022 11:39:25 -0500 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBCAB14000 for ; Mon, 5 Dec 2022 08:38:12 -0800 (PST) Received: by mail-ed1-x534.google.com with SMTP id m19so16541654edj.8 for ; Mon, 05 Dec 2022 08:38:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zdoZ3Re0757L2mwn1KYvl/6yc6DEIjLF3AShLHyNWWM=; b=JMKm0kKI+noLyReu0/ATNV8+wCuvNS7JEXXZjPRL1OtYRGio4ViGJUflWj7brVgXas hHkilrRB8y+qxQUqknlsPwjsVvkLy+tBUiEA6qBRKVaAS9poy8CR/yCUkVC9vrA5quks 9g8uu6qPxj+J5aokqc31cjTXxXvw9zAMzoajM8F7Tn61q8Xc4WuqzPy2dDvNLUVpu0uB XKjp0aBeypxdLgtp9c3OCAxcMjsB1AdIilVFaCSB4AgqgU5Jx9wbnYWKoAeEGigfD8WU Z8JrPjAHGx8MUNqKT2BsqWJ4L5rOC5FLsd4MkwiveXOp1ONLKg7djDPU2safEJzmiWLo hqpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zdoZ3Re0757L2mwn1KYvl/6yc6DEIjLF3AShLHyNWWM=; b=KR6jN1nucECQYVPFGK/whs8dVhqsRACVgzfKxIxRwI0LEWA0SGjSuNXIr5dOvfNpgq Uq+Zbv4fN9MWA2o1holc5OgaelJNGD4HsX+oYVGb0YUmoulxu0TTuYD+cXFMsLBl2GIV 92kWCqG/JYiJxUZa0XmibySFV0jy52kwlK5I9zNF80laMyaFOSBNvZuOEDPbZ/wfqXPW HvxxxDfxtE0b44qQEa4YafGTDZFo2lJUTbRBAV1qKVVhiMaANN6+tHucHH5Ktuh0+xg1 MR6qPJnM70l4s8hMvg/3QrUwKx8v50schtGl26unIAKXk4P1BjuwF3IrDPK8ot9pLFhG q7GA== X-Gm-Message-State: ANoB5pnqzp7wUQVBBt/J17wagk769AcssYWHbwbO2LcCk1hSEE7PLsnd OHdR2mVuqmA6cJmbqk2vpxPyMA== X-Google-Smtp-Source: AA0mqf54xMct7ysrBdlruu+pyTFTsdOmHgBo3Vbycr9HMKr2aqqvpzU3+jbN410wfqAOZv8Wq/9jMA== X-Received: by 2002:aa7:c585:0:b0:46b:635a:ed8f with SMTP id g5-20020aa7c585000000b0046b635aed8fmr27387734edq.406.1670258292371; Mon, 05 Dec 2022 08:38:12 -0800 (PST) Received: from prec5560.localdomain (ip5f58f364.dynamic.kabel-deutschland.de. [95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:11 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Cc: Konrad Dybcio Subject: [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells Date: Mon, 5 Dec 2022 17:37:51 +0100 Message-Id: <20221205163754.221139-9-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use two interconnect cells in order to optionally support a path tag. Signed-off-by: Robert Foss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 805d53d91952..434f8e8b12c1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 { config_noc: interconnect@1500000 { compatible =3D "qcom,sm8350-config-noc"; reg =3D <0 0x01500000 0 0xa580>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 mc_virt: interconnect@1580000 { compatible =3D "qcom,sm8350-mc-virt"; reg =3D <0 0x01580000 0 0x1000>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 system_noc: interconnect@1680000 { compatible =3D "qcom,sm8350-system-noc"; reg =3D <0 0x01680000 0 0x1c200>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 aggre1_noc: interconnect@16e0000 { compatible =3D "qcom,sm8350-aggre1-noc"; reg =3D <0 0x016e0000 0 0x1f180>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 aggre2_noc: interconnect@1700000 { compatible =3D "qcom,sm8350-aggre2-noc"; reg =3D <0 0x01700000 0 0x33000>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 mmss_noc: interconnect@1740000 { compatible =3D "qcom,sm8350-mmss-noc"; reg =3D <0 0x01740000 0 0x1f080>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 lpass_ag_noc: interconnect@3c40000 { compatible =3D "qcom,sm8350-lpass-ag-noc"; reg =3D <0 0x03c40000 0 0xf080>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 compute_noc: interconnect@a0c0000{ compatible =3D "qcom,sm8350-compute-noc"; reg =3D <0 0x0a0c0000 0 0xa180>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 @@ -1620,8 +1620,8 @@ ipa: ipa@1e40000 { clocks =3D <&rpmhcc RPMH_IPA_CLK>; clock-names =3D "core"; =20 - interconnects =3D <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnects =3D <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names =3D "memory", "config"; =20 @@ -1661,7 +1661,7 @@ mpss: remoteproc@4080000 { <&rpmhpd SM8350_MSS>; power-domain-names =3D "cx", "mss"; =20 - interconnects =3D <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + interconnects =3D <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1 0>; =20 memory-region =3D <&pil_modem_mem>; =20 @@ -2239,7 +2239,7 @@ cdsp: remoteproc@98900000 { <&rpmhpd SM8350_MXC>; power-domain-names =3D "cx", "mxc"; =20 - interconnects =3D <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + interconnects =3D <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 = 0>; =20 memory-region =3D <&pil_cdsp_mem>; =20 @@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 { dc_noc: interconnect@90c0000 { compatible =3D "qcom,sm8350-dc-noc"; reg =3D <0 0x090c0000 0 0x4200>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 gem_noc: interconnect@9100000 { compatible =3D "qcom,sm8350-gem-noc"; reg =3D <0 0x09100000 0 0xb4000>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E717C47089 for ; Mon, 5 Dec 2022 16:40:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233255AbiLEQko (ORCPT ); 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[95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:13 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes Date: Mon, 5 Dec 2022 17:37:52 +0100 Message-Id: <20221205163754.221139-10-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++- 1 file changed, 195 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 434f8e8b12c1..fb1c616c5e89 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ =20 +#include #include #include #include @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 { }; }; =20 + mdss: mdss@ae00000 { + compatible =3D "qcom,sm8350-mdss"; + reg =3D <0 0x0ae00000 0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + power-domains =3D <&dispcc MDSS_GDSC>; + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x820 0x402>; + + status =3D "disabled"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm8350-dpu"; + reg =3D <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, + <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + phys =3D <&dsi0_phy>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* TODO: opp-200000000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz =3D /bits/ 64 <345000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-5nm-8350"; + reg =3D <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,sm8350-dispcc"; reg =3D <0 0x0af00000 0 0x10000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <0>, - <0>, - <0>, - <0>, + <&dsi0_phy 0>, <&dsi0_phy 1>, + <0>, <0>, <0>, <0>; clock-names =3D "bi_tcxo", @@ -2558,6 +2748,7 @@ dispcc: clock-controller@af00000 { #power-domain-cells =3D <1>; =20 power-domains =3D <&rpmhpd SM8350_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; }; =20 adsp: remoteproc@17300000 { --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAB2DC4332F for ; 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[95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:15 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Date: Mon, 5 Dec 2022 17:37:53 +0100 Message-Id: <20221205163754.221139-11-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the display subsystem and the dsi0 output for the sm8350-hdk board. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8350-hdk.dts index e6deb08c6da0..39462c659c58 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -213,10 +213,32 @@ &cdsp { firmware-name =3D "qcom/sm8350/cdsp.mbn"; }; =20 +&dispcc { + status =3D "okay"; +}; + +&dsi0 { + vdda-supply =3D <&vreg_l6b_1p2>; + status =3D "okay"; +}; + +&dsi0_phy { + vdds-supply =3D <&vreg_l5b_0p88>; + status =3D "okay"; +}; + &gpi_dma1 { status =3D "okay"; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_mdp { + status =3D "okay"; +}; + &mpss { status =3D "okay"; firmware-name =3D "qcom/sm8350/modem.mbn"; --=20 2.34.1 From nobody Thu Sep 18 15:29:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB5F2C4332F for ; Mon, 5 Dec 2022 16:40:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233270AbiLEQk5 (ORCPT ); Mon, 5 Dec 2022 11:40:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233032AbiLEQjf (ORCPT ); Mon, 5 Dec 2022 11:39:35 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E1C6205E1 for ; Mon, 5 Dec 2022 08:38:18 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id vv4so29147926ejc.2 for ; Mon, 05 Dec 2022 08:38:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bEH3pnZJvLD0zwCY2qegZFliLhqKwSFLXksz2qDwd0o=; b=OeTzndGKys7w4AIe7cNLcW0+3q2MjOuFI3Oaxw91IHy+Hrd14F4rsHgtZ7jURzrf3a SXu+jbQKQangMprAENpevL8aDEfl14ADH74gsCdGHooYwswCkqlUm0LRFi1D9CM5CO5/ itbAcg+nHqTqkq7WgwzwAFOj21dVAk/E+r+yESDRaxV5WGTyTiaDBDb/+pLX21vS7uT0 0IkS6OKzLkasHG3rzd7bAYDh25fDABh6lmLWkIgGknwISkS/pqb1l3Q5/1sNM3/ZXm60 rzCxmgAoTIs9pstNprlHSwewef2vK7FAApNTiNrcPtsKTsrbGUVZ6Z4MA92LlamlKNoo 2c4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bEH3pnZJvLD0zwCY2qegZFliLhqKwSFLXksz2qDwd0o=; b=Lh+qpYOHb14AZiRSthMyFXtfE4baqHMKTKp1mdXSqZOe4KzhXz8sgOLRCGBEGcebeh E5DK/TZE1JfphcOMOKd896OFgoBGkGlLrkWqIAvNgtnKT/f4XsuAXsc4t1KoRABba5Tx d8nRD20X0j6cQa/q1mzbkKxHyCI4DRltyRMGAEoXkcChQIrTVCr2QQoq8G9PBXwCJ2AH tJVxskAdVF7rzVmq3ixx9tDo1gI1FXNZLljNJqxMpvGtR927RUHUtwNUj2scz6WZcfcL Ifa5tjw6m48gcNvyJxM8OBzWGHfMReR78xOBVhLlPx9JHcYxgdg1YdfLXBNKB/w8ZQ2R B5+A== X-Gm-Message-State: ANoB5pnYCqHIgCGT4WddfJiWWhIw7EpCqMs+Z0Ah1c/iD2s4olu+BGTH pSaiR6DE+MZts2Jg2oA1H3Zo9A== X-Google-Smtp-Source: AA0mqf5WYzukFU7nm0KUB5VLtChKqyNpg7pnF3phCbKSYsTcTDGnaSR5YLlGBt/GnTwwF9GbXEH7/g== X-Received: by 2002:a17:906:5649:b0:7ad:a2ef:c62 with SMTP id v9-20020a170906564900b007ada2ef0c62mr8664821ejr.126.1670258297724; Mon, 05 Dec 2022 08:38:17 -0800 (PST) Received: from prec5560.localdomain (ip5f58f364.dynamic.kabel-deutschland.de. [95.88.243.100]) by smtp.gmail.com with ESMTPSA id e21-20020a170906315500b007bed316a6d9sm6413610eje.18.2022.12.05.08.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Dec 2022 08:38:17 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, robert.foss@linaro.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Date: Mon, 5 Dec 2022 17:37:54 +0100 Message-Id: <20221205163754.221139-12-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205163754.221139-1-robert.foss@linaro.org> References: <20221205163754.221139-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip. In order to toggle the board to enable the HDMI output, switch #7 & #8 on the rightmost multi-switch package have to be toggled to On. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105 ++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8350-hdk.dts index 39462c659c58..3aa4ca8271e5 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -20,6 +20,17 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con: endpoint { + remote-endpoint =3D <<9611_out>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vph_pwr"; @@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator { regulator-always-on; regulator-boot-on; }; + + lt9611_1v2: lt9611-1v2-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "LT9611_1V2"; + + vin-supply =3D <&vph_pwr>; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + gpio =3D <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "LT9611_3V3"; + + vin-supply =3D <&vreg_bob>; + gpio =3D <&tlmm 47 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; }; =20 &adsp { @@ -220,6 +256,15 @@ &dispcc { &dsi0 { vdda-supply =3D <&vreg_l6b_1p2>; status =3D "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <<9611_a>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; }; =20 &dsi0_phy { @@ -231,6 +276,46 @@ &gpi_dma1 { status =3D "okay"; }; =20 +&i2c15 { + clock-frequency =3D <400000>; + status =3D "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible =3D "lontium,lt9611uxc"; + reg =3D <0x2b>; + + interrupts-extended =3D <&tlmm 50 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&tlmm 48 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <<9611_1v2>; + vcc-supply =3D <<9611_3v3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <<9611_state>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lt9611_a: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + + port@2 { + reg =3D <2>; + + lt9611_out: endpoint { + remote-endpoint =3D <&hdmi_con>; + }; + }; + }; + }; +}; + &mdss { status =3D "okay"; }; @@ -248,6 +333,10 @@ &qupv3_id_0 { status =3D "okay"; }; =20 +&qupv3_id_2 { + status =3D "okay"; +}; + &slpi { status =3D "okay"; firmware-name =3D "qcom/sm8350/slpi.mbn"; @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state { drive-strength =3D <2>; output-low; }; + + lt9611_state: lt9611-state { + lt9611_rst_pin { + pins =3D "gpio48"; + function =3D "normal"; + + output-high; + input-disable; + }; + + lt9611_irq_pin { + pins =3D "gpio50"; + function =3D "gpio"; + bias-disable; + }; + }; }; --=20 2.34.1