From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 134D4C4708E for ; Mon, 5 Dec 2022 06:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231526AbiLEG6Z (ORCPT ); Mon, 5 Dec 2022 01:58:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230092AbiLEG6S (ORCPT ); Mon, 5 Dec 2022 01:58:18 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14D1564CB; Sun, 4 Dec 2022 22:58:14 -0800 (PST) X-UUID: 5f5c10f909ca4b99938310a92920325c-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1WMPHgGT2Vc06cNDWGV7eQXxRmPqVm37oCGD2yTJxvQ=; b=DOLBopSdwrxYRACR642xEdclstPqvpiA15BQILD3PwlcKb9dYkhO9ZHgwReZgPTj2hG5d2I1MM+cmcg9/YvWSSMIlCY7IM3JaswwpivhfEDHtEniCOitZogRYfClAFMRbcmQX52eus4zpeskonYOegjmiHzzEmoEUBq+AvXYudQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:0cc62d45-d4b9-46d9-9f18-81fe86a57a79,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.14,REQID:0cc62d45-d4b9-46d9-9f18-81fe86a57a79,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:dcaaed0,CLOUDID:af1f916c-41fe-47b6-8eb4-ec192dedaf7d,B ulkID:221205145809XW7S9LTG,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 5f5c10f909ca4b99938310a92920325c-20221205 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1479084019; Mon, 05 Dec 2022 14:58:09 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:09 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:08 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 1/9] spi: mtk-snfi: Add snfi support for MT7986 IC Date: Mon, 5 Dec 2022 14:57:48 +0800 Message-ID: <20221205065756.26875-2-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add snfi support for MT7986 IC. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index d66bf9762557..fa8412ba20e2 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -126,7 +126,8 @@ #define STR_DATA BIT(0) =20 #define NFI_STA 0x060 -#define NFI_NAND_FSM GENMASK(28, 24) +#define NFI_NAND_FSM_7622 GENMASK(28, 24) +#define NFI_NAND_FSM_7986 GENMASK(29, 23) #define NFI_FSM GENMASK(19, 16) #define READ_EMPTY BIT(12) =20 @@ -158,6 +159,7 @@ #define MAS_WR GENMASK(5, 3) #define MAS_RDDLY GENMASK(2, 0) #define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) +#define NFI_MASTERSTA_MASK_7986 3 =20 // SNFI registers #define SNF_MAC_CTL 0x500 @@ -220,6 +222,11 @@ =20 static const u8 mt7622_spare_sizes[] =3D { 16, 26, 27, 28 }; =20 +static const u8 mt7986_spare_sizes[] =3D { + 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, + 74 +}; + struct mtk_snand_caps { u16 sector_size; u16 max_sectors; @@ -230,6 +237,7 @@ struct mtk_snand_caps { bool bbm_swap; bool empty_page_check; u32 mastersta_mask; + u32 nandfsm_mask; =20 const u8 *spare_sizes; u32 num_spare_size; @@ -244,6 +252,7 @@ static const struct mtk_snand_caps mt7622_snand_caps = =3D { .bbm_swap =3D false, .empty_page_check =3D false, .mastersta_mask =3D NFI_MASTERSTA_MASK_7622, + .nandfsm_mask =3D NFI_NAND_FSM_7622, .spare_sizes =3D mt7622_spare_sizes, .num_spare_size =3D ARRAY_SIZE(mt7622_spare_sizes) }; @@ -257,10 +266,25 @@ static const struct mtk_snand_caps mt7629_snand_caps = =3D { .bbm_swap =3D true, .empty_page_check =3D false, .mastersta_mask =3D NFI_MASTERSTA_MASK_7622, + .nandfsm_mask =3D NFI_NAND_FSM_7622, .spare_sizes =3D mt7622_spare_sizes, .num_spare_size =3D ARRAY_SIZE(mt7622_spare_sizes) }; =20 +static const struct mtk_snand_caps mt7986_snand_caps =3D { + .sector_size =3D 1024, + .max_sectors =3D 8, + .fdm_size =3D 8, + .fdm_ecc_size =3D 1, + .fifo_size =3D 64, + .bbm_swap =3D true, + .empty_page_check =3D true, + .mastersta_mask =3D NFI_MASTERSTA_MASK_7986, + .nandfsm_mask =3D NFI_NAND_FSM_7986, + .spare_sizes =3D mt7986_spare_sizes, + .num_spare_size =3D ARRAY_SIZE(mt7986_spare_sizes) +}; + struct mtk_snand_conf { size_t page_size; size_t oob_size; @@ -360,7 +384,7 @@ static int mtk_nfi_reset(struct mtk_snand *snf) } =20 ret =3D readl_poll_timeout(snf->nfi_base + NFI_STA, val, - !(val & (NFI_FSM | NFI_NAND_FSM)), 0, + !(val & (NFI_FSM | snf->caps->nandfsm_mask)), 0, SNFI_POLL_INTERVAL); if (ret) { dev_err(snf->dev, "Failed to reset NFI\n"); @@ -1295,6 +1319,7 @@ static irqreturn_t mtk_snand_irq(int irq, void *id) static const struct of_device_id mtk_snand_ids[] =3D { { .compatible =3D "mediatek,mt7622-snand", .data =3D &mt7622_snand_caps }, { .compatible =3D "mediatek,mt7629-snand", .data =3D &mt7629_snand_caps }, + { .compatible =3D "mediatek,mt7986-snand", .data =3D &mt7986_snand_caps }, {}, }; =20 --=20 2.25.1 From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5468C47088 for ; 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Mon, 5 Dec 2022 14:58:09 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 2/9] spi: mtk-snfi: Change default page format to setup default setting Date: Mon, 5 Dec 2022 14:57:49 +0800 Message-ID: <20221205065756.26875-3-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Change default page format to setup default setting since the sector size 1024 on MT7986 will lead to probe fail. Signed-off-by: Xiangsheng Hou --- drivers/spi/spi-mtk-snfi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index fa8412ba20e2..719fc6f53ab1 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -1430,8 +1430,7 @@ static int mtk_snand_probe(struct platform_device *pd= ev) =20 // setup an initial page format for ops matching page_cache_op template // before ECC is called. - ret =3D mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, - ms->caps->spare_sizes[0]); + ret =3D mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64); if (ret) { dev_err(ms->dev, "failed to set initial page format\n"); goto disable_clk; --=20 2.25.1 From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC149C63703 for ; Mon, 5 Dec 2022 06:58:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231461AbiLEG6g (ORCPT ); Mon, 5 Dec 2022 01:58:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230209AbiLEG6S (ORCPT ); Mon, 5 Dec 2022 01:58:18 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B767364F9; Sun, 4 Dec 2022 22:58:16 -0800 (PST) X-UUID: dc9af5796c5a42848445a19d7073cb8b-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=eIBjEN/FPdq/8jwIM30UAE6rJrZxiQ0OkReuKlIIvFI=; b=UjLJzXj0LVG/V7jiiKY0FvJ7dGQtXKnHXb97DuezmFghQmS3qTpjLElJCuIZTYqfe8EUhSLNBnSlJqzqHYgOOmHmX+Nj9rsv91nN/4+cintMbRf9s8TEg+mNX32+/liwZaIvftXgq+g03EdQ6kpwU/7xlhi/dASlwY97JmUns7Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:89e77a85-dbf3-41ef-995e-e350c322fe12,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:89e77a85-dbf3-41ef-995e-e350c322fe12,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:7f3aae30-2938-482e-aafd-98d66723b8a9,B ulkID:221205145812ZHY4M186,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: dc9af5796c5a42848445a19d7073cb8b-20221205 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 138225994; Mon, 05 Dec 2022 14:58:12 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:11 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:10 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 3/9] spi: mtk-snfi: Add optional nfi_hclk which needed for MT7986 Date: Mon, 5 Dec 2022 14:57:50 +0800 Message-ID: <20221205065756.26875-4-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add optional nfi_hclk which needed for MT7986. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 719fc6f53ab1..85644308df23 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -297,6 +297,7 @@ struct mtk_snand { struct device *dev; struct clk *nfi_clk; struct clk *pad_clk; + struct clk *nfi_hclk; void __iomem *nfi_base; int irq; struct completion op_done; @@ -1339,7 +1340,16 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) dev_err(ms->dev, "unable to enable pad clk\n"); goto err1; } + ret =3D clk_prepare_enable(ms->nfi_hclk); + if (ret) { + dev_err(ms->dev, "unable to enable nfi hclk\n"); + goto err2; + } + return 0; + +err2: + clk_disable_unprepare(ms->pad_clk); err1: clk_disable_unprepare(ms->nfi_clk); return ret; @@ -1347,6 +1357,7 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) =20 static void mtk_snand_disable_clk(struct mtk_snand *ms) { + clk_disable_unprepare(ms->nfi_hclk); clk_disable_unprepare(ms->pad_clk); clk_disable_unprepare(ms->nfi_clk); } @@ -1401,6 +1412,13 @@ static int mtk_snand_probe(struct platform_device *p= dev) goto release_ecc; } =20 + ms->nfi_hclk =3D devm_clk_get_optional(&pdev->dev, "nfi_hclk"); + if (IS_ERR(ms->nfi_hclk)) { + ret =3D PTR_ERR(ms->nfi_hclk); + dev_err(&pdev->dev, "unable to get nfi_hclk, err =3D %d\n", ret); + goto release_ecc; + } + ret =3D mtk_snand_enable_clk(ms); if (ret) goto release_ecc; --=20 2.25.1 From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5BB9C47089 for ; Mon, 5 Dec 2022 06:58:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231577AbiLEG6d (ORCPT ); Mon, 5 Dec 2022 01:58:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230151AbiLEG6S (ORCPT ); Mon, 5 Dec 2022 01:58:18 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EB956542; Sun, 4 Dec 2022 22:58:17 -0800 (PST) X-UUID: 5792ba6f3fff4e35940bc549c533325b-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Lzw4oSEiFeMdkofxiQoJmN6XMwM8R/ZldMoLGp/LTVE=; b=tgv+VW32vFcT26eLQOv8uMKFJIQDpXlQlapfQQEG9kM9oFWPy7yQ4FEDMggpsy4LoXYJDlCxoejzxQ6/+opS0K4BhDcZkq2Zd7q74R0B3NSTrgMDXCisBFc7zMOFUn+XVkpGYFA+xI/0CGncecU7p413UX8PQXgtpvxDteSv6ps=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:23161778-1443-4350-aa90-4a636c74514f,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:23161778-1443-4350-aa90-4a636c74514f,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:dc3aae30-2938-482e-aafd-98d66723b8a9,B ulkID:221205145815JNP9YMBV,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 5792ba6f3fff4e35940bc549c533325b-20221205 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 893488993; Mon, 05 Dec 2022 14:58:13 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:12 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:11 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 4/9] mtd: nand: ecc-mtk: Add ECC support fot MT7986 IC Date: Mon, 5 Dec 2022 14:57:51 +0800 Message-ID: <20221205065756.26875-5-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ECC support fot MT7986 IC. Signed-off-by: Xiangsheng Hou --- drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c index 9f9b201fe706..c2f6cfa76a04 100644 --- a/drivers/mtd/nand/ecc-mtk.c +++ b/drivers/mtd/nand/ecc-mtk.c @@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] =3D { 4, 6, 8, 10, 12 }; =20 +static const u8 ecc_strength_mt7986[] =3D { + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 +}; + enum mtk_ecc_regs { ECC_ENCPAR00, ECC_ENCIRQ_EN, @@ -483,6 +487,17 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = =3D { .pg_irq_sel =3D 0, }; =20 +static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 =3D { + .err_mask =3D 0x1f, + .err_shift =3D 8, + .ecc_strength =3D ecc_strength_mt7986, + .ecc_regs =3D mt2712_ecc_regs, + .num_ecc_strength =3D 11, + .ecc_mode_shift =3D 5, + .parity_bits =3D 14, + .pg_irq_sel =3D 1, +}; + static const struct of_device_id mtk_ecc_dt_match[] =3D { { .compatible =3D "mediatek,mt2701-ecc", @@ -493,6 +508,9 @@ static const struct of_device_id mtk_ecc_dt_match[] =3D= { }, { .compatible =3D "mediatek,mt7622-ecc", .data =3D &mtk_ecc_caps_mt7622, + }, { + .compatible =3D "mediatek,mt7986-ecc", + .data =3D &mtk_ecc_caps_mt7986, }, {}, }; --=20 2.25.1 From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2251C4321E for ; Mon, 5 Dec 2022 06:58:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231545AbiLEG6k (ORCPT ); Mon, 5 Dec 2022 01:58:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231443AbiLEG6V (ORCPT ); Mon, 5 Dec 2022 01:58:21 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1EAD646B; Sun, 4 Dec 2022 22:58:19 -0800 (PST) X-UUID: 05e94d46f75b4c538019b4df05fc0601-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Rzm8NGnhC/Y3p58483tZdX6IHSByPcsSolFg96uJoLs=; b=bRRlXhlH+69fp41mPgZzEIl2hpkS7ENYBFwDCc4JVSliDZGasouLuZKeMP+/ssxvC/GMHI1JCqwoJATU3iSbKEuts87stRqhAfnuW5sd3cO6rPcUPQaOvx8nVFtX40nCiO8Sg4rh/lUZg/evVN1qO3GhugFPF/q8awamowlauIw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:99061f05-b8d0-4ba6-afa9-87168a139706,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:dcaaed0,CLOUDID:eb3aae30-2938-482e-aafd-98d66723b8a9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 05e94d46f75b4c538019b4df05fc0601-20221205 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2062261961; Mon, 05 Dec 2022 14:58:14 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:13 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:12 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 5/9] dt-bindings: spi: mtk-snfi: Add compatible for MT7986 Date: Mon, 5 Dec 2022 14:57:52 +0800 Message-ID: <20221205065756.26875-6-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" 1. Add dt-bindings documentation of SPI NAND controller for MediaTek MT7986 SoC platform. 2. Add optional nfi_hclk property which needed for MT7986. Signed-off-by: Xiangsheng Hou Reviewed-by: Krzysztof Kozlowski --- .../bindings/spi/mediatek,spi-mtk-snfi.yaml | 51 +++++++++++++++---- 1 file changed, 42 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.ya= ml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index 6e6e02c91780..bab23f1b11fd 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -18,14 +18,12 @@ description: | using the accompanying ECC engine. There should be only one spi slave device following generic spi bindings. =20 -allOf: - - $ref: /schemas/spi/spi-controller.yaml# - properties: compatible: enum: - mediatek,mt7622-snand - mediatek,mt7629-snand + - mediatek,mt7986-snand =20 reg: items: @@ -36,14 +34,12 @@ properties: - description: NFI interrupt =20 clocks: - items: - - description: clock used for the controller - - description: clock used for the SPI bus + minItems: 2 + maxItems: 3 =20 clock-names: - items: - - const: nfi_clk - - const: pad_clk + minItems: 2 + maxItems: 3 =20 nand-ecc-engine: description: device-tree node of the accompanying ECC engine. @@ -57,6 +53,43 @@ required: - clock-names - nand-ecc-engine =20 +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + - if: + properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + - if: + properties: + compatible: + enum: + - mediatek,mt7986-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + - description: clock used for the AHB bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + - const: nfi_hclk + unevaluatedProperties: false =20 examples: --=20 2.25.1 From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AF9BC4321E for ; Mon, 5 Dec 2022 06:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231643AbiLEG6n (ORCPT ); Mon, 5 Dec 2022 01:58:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231436AbiLEG6V (ORCPT ); Mon, 5 Dec 2022 01:58:21 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 641A7647D; Sun, 4 Dec 2022 22:58:20 -0800 (PST) X-UUID: f3f6189c7c9743579a9cd20b8f5cc3ae-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VBL576pkrtXP6/de0wvgMxEdL4WcGZ/83O47rZMO8Rk=; b=oHSTZvt03VVSvF2A3DUmwDUbRvY+Z1uj+rHD6rqDXWUiUun/clqHAzUjNFuwTybfKJq+cTod32mdLEpJDNbrruxmROXanSIU3hVp9m39Zyj4/qYinIp72DjYi7QcvP9eVqKyUbFLLQpbt6Gu54wlsze978Cj2FPgwXwF3Tyi2Dw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:db634ceb-8c0e-433f-ad45-f045fb133d5b,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.14,REQID:db634ceb-8c0e-433f-ad45-f045fb133d5b,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:dcaaed0,CLOUDID:4a3bae30-2938-482e-aafd-98d66723b8a9,B ulkID:2212051458185W24MXAW,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f3f6189c7c9743579a9cd20b8f5cc3ae-20221205 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 924111099; Mon, 05 Dec 2022 14:58:16 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:14 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:13 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 6/9] spi: mtk-snfi: Add snfi sample delay and read latency adjustment Date: Mon, 5 Dec 2022 14:57:53 +0800 Message-ID: <20221205065756.26875-7-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add snfi sample delay and read latency adjustment which can get from dts property. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 85644308df23..32a9a817869c 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -195,6 +195,8 @@ #define DATA_READ_MODE_X4 2 #define DATA_READ_MODE_DUAL 5 #define DATA_READ_MODE_QUAD 6 +#define DATA_READ_LATCH_LAT GENMASK(9, 8) +#define DATA_READ_LATCH_LAT_S 8 #define PG_LOAD_CUSTOM_EN BIT(7) #define DATARD_CUSTOM_EN BIT(6) #define CS_DESELECT_CYC_S 0 @@ -205,6 +207,9 @@ =20 #define SNF_DLY_CTL3 0x548 #define SFCK_SAM_DLY_S 0 +#define SFCK_SAM_DLY GENMASK(5, 0) +#define SFCK_SAM_DLY_TOTAL 9 +#define SFCK_SAM_DLY_RANGE 47 =20 #define SNF_STA_CTL1 0x550 #define CUS_PG_DONE BIT(28) @@ -1368,6 +1373,7 @@ static int mtk_snand_probe(struct platform_device *pd= ev) const struct of_device_id *dev_id; struct spi_controller *ctlr; struct mtk_snand *ms; + u32 val =3D 0; int ret; =20 dev_id =3D of_match_node(mtk_snand_ids, np); @@ -1446,6 +1452,16 @@ static int mtk_snand_probe(struct platform_device *p= dev) // switch to SNFI mode nfi_write32(ms, SNF_CFG, SPI_MODE); =20 + ret =3D of_property_read_u32(np, "rx-sample-delay-ns", &val); + if (!ret) + nfi_rmw32(ms, SNF_DLY_CTL3, SFCK_SAM_DLY, + val * SFCK_SAM_DLY_RANGE / SFCK_SAM_DLY_TOTAL); + + ret =3D of_property_read_u32(np, "mediatek,rx-latch-latency", &val); + if (!ret) + nfi_rmw32(ms, SNF_MISC_CTL, DATA_READ_LATCH_LAT, + val << DATA_READ_LATCH_LAT_S); + // setup an initial page format for ops matching page_cache_op template // before ECC is called. ret =3D mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64); --=20 2.25.1 From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0117AC4321E for ; Mon, 5 Dec 2022 06:58:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231611AbiLEG6w (ORCPT ); Mon, 5 Dec 2022 01:58:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231497AbiLEG6Y (ORCPT ); Mon, 5 Dec 2022 01:58:24 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B41D96585; Sun, 4 Dec 2022 22:58:22 -0800 (PST) X-UUID: b207963b87514c1c892af3466435d722-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=b2WSZ3CeVel7jtK8eB9zexq5s0JpdBbozdst3aQS8gk=; b=c/i6iwBJGQicGSiS2ceTvhTu44Z+zLUK8LGR9u69OEUIl/FaSa3i03VsuQbnkBcC8BbNyEYygKdUWabgHEKsPZypNv5RAq/lry5mrVKGIfduRmO9fy4/TPSfVPRmso76h5SK07MM27laFOMNvAmjavNlaaB1AU5f+7Fj/jZZcN4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:e4695202-b347-4f33-b499-ff88edb05658,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:dcaaed0,CLOUDID:b8a1291f-5e1d-4ab5-ab8e-3e04efc02b30,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b207963b87514c1c892af3466435d722-20221205 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1698312840; Mon, 05 Dec 2022 14:58:17 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:15 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:14 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 7/9] dt-bindings: spi: mtk-snfi: Add read latch latency property Date: Mon, 5 Dec 2022 14:57:54 +0800 Message-ID: <20221205065756.26875-8-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add mediatek,rx-latch-latency property which adjust read delay in the unit of clock cycle. Signed-off-by: Xiangsheng Hou Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.ya= ml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index bab23f1b11fd..6e6ff8d73fcd 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -45,6 +45,13 @@ properties: description: device-tree node of the accompanying ECC engine. $ref: /schemas/types.yaml#/definitions/phandle =20 + mediatek,rx-latch-latency: + description: Rx delay to sample data with this value, the value + unit is clock cycle. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + required: - compatible - reg --=20 2.25.1 From nobody Sun Apr 28 11:50:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAAC4C4321E for ; Mon, 5 Dec 2022 06:58:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231616AbiLEG64 (ORCPT ); Mon, 5 Dec 2022 01:58:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231532AbiLEG61 (ORCPT ); Mon, 5 Dec 2022 01:58:27 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B867465A7; Sun, 4 Dec 2022 22:58:23 -0800 (PST) X-UUID: 4eeddb01bf5e41fbbb9e2593b173e41e-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=s0ldFyfllwtQjC5cbsKPxF4rBQNdmUSYFbsQQRSbrtQ=; b=ELXNIeajuVFcFjWekJtDtE8CKsQ2RWSr5/q+rFSBu+5m8O5aXtN7Edq2iHGtWpDNRljHYocoW3CfE/EbE2v1TXX6vNbfRqHqA07ybQ6pRzVghWXMKOpGAMBmkDoiU6iQy+557XgD+aB4AHsWPTV3SJhVEE/5zfwZ1C5GCLN2ZrU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:8fc8026a-9859-4149-86c6-4972aafe051c,IP:0,U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:5d3bae30-2938-482e-aafd-98d66723b8a9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 4eeddb01bf5e41fbbb9e2593b173e41e-20221205 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 305925263; Mon, 05 Dec 2022 14:58:18 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:16 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:16 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 8/9] dt-bindings: mtd: Split ECC engine with rawnand controller Date: Mon, 5 Dec 2022 14:57:55 +0800 Message-ID: <20221205065756.26875-9-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" 1. Split MediaTek ECC engine with rawnand controller and convert to YAML schema. 2. Change the existing node name in order to match NAND controller DT bindings. Signed-off-by: Xiangsheng Hou --- .../bindings/mtd/mediatek,mtk-nfc.yaml | 171 +++++++++++++++++ .../mtd/mediatek,nand-ecc-engine.yaml | 62 ++++++ .../devicetree/bindings/mtd/mtk-nand.txt | 176 ------------------ arch/arm/boot/dts/mt2701.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- 6 files changed, 236 insertions(+), 179 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.= yaml create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,nand-ecc= -engine.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml b/= Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml new file mode 100644 index 000000000000..2b1c92edc9d0 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC) + +maintainers: + - Xiangsheng Hou + +properties: + compatible: + enum: + - mediatek,mt2701-nfc + - mediatek,mt2712-nfc + - mediatek,mt7622-nfc + + reg: + items: + - description: Base physical address and size of NFI. + + interrupts: + items: + - description: NFI interrupt + + clocks: + items: + - description: clock used for the controller + - description: clock used for the pad + + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + ecc-engine: true + + partitions: + $ref: mtd.yaml# + +allOf: + - $ref: nand-controller.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt2701-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + reg: + minimum: 0 + maximum: 1 + nand-ecc-mode: + const: hw + nand-ecc-step-size: + enum: [ 512, 1024 ] + nand-ecc-strength: + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, + 40, 44, 48, 52, 56, 60] + + - if: + properties: + compatible: + contains: + const: mediatek,mt2712-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + reg: + minimum: 0 + maximum: 1 + nand-ecc-mode: + const: hw + nand-ecc-step-size: + enum: [ 512, 1024 ] + nand-ecc-strength: + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, + 40, 44, 48, 52, 56, 60, 68, 72, 80] + + - if: + properties: + compatible: + contains: + const: mediatek,mt7622-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + reg: + minimum: 0 + maximum: 1 + nand-ecc-mode: + const: hw + nand-ecc-step-size: + const: 512 + nand-ecc-strength: + enum: [4, 6, 8, 10, 12] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ecc-engine + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + nand-controller@1100d000 { + compatible =3D "mediatek,mt2701-nfc"; + reg =3D <0 0x1100d000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names =3D "nfi_clk", "pad_clk"; + ecc-engine =3D <&bch>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nand@0 { + reg =3D <0>; + + nand-on-flash-bbt; + nand-ecc-mode =3D "hw"; + nand-ecc-step-size =3D <1024>; + nand-ecc-strength =3D <24>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + preloader@0 { + label =3D "pl"; + read-only; + reg =3D <0x0 0x400000>; + }; + android@400000 { + label =3D "android"; + reg =3D <0x400000 0x12c00000>; + }; + }; + }; + }; + + bch: ecc@1100e000 { + compatible =3D "mediatek,mt2701-ecc"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI_ECC>; + clock-names =3D "nfiecc_clk"; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine= .yaml b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml new file mode 100644 index 000000000000..b13d801eda76 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs NAND ECC engine + +maintainers: + - Xiangsheng Hou + +description: | + MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. + +properties: + compatible: + enum: + - mediatek,mt2701-ecc + - mediatek,mt2712-ecc + - mediatek,mt7622-ecc + + reg: + items: + - description: Base physical address and size of ECC. + + interrupts: + items: + - description: ECC interrupt + + clocks: + maxItems: 1 + + clock-names: + const: nfiecc_clk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + bch: ecc@1100e000 { + compatible =3D "mediatek,mt2701-ecc"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI_ECC>; + clock-names =3D "nfiecc_clk"; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documenta= tion/devicetree/bindings/mtd/mtk-nand.txt deleted file mode 100644 index 839ea2f93d04..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt +++ /dev/null @@ -1,176 +0,0 @@ -MTK SoCs NAND FLASH controller (NFC) DT binding - -This file documents the device tree bindings for MTK SoCs NAND controllers. -The functional split of the controller requires two drivers to operate: -the nand controller interface driver and the ECC engine driver. - -The hardware description for both devices must be captured as device -tree nodes. - -1) NFC NAND Controller Interface (NFI): -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The first part of NFC is NAND Controller Interface (NFI) HW. -Required NFI properties: -- compatible: Should be one of - "mediatek,mt2701-nfc", - "mediatek,mt2712-nfc", - "mediatek,mt7622-nfc". -- reg: Base physical address and size of NFI. -- interrupts: Interrupts of NFI. -- clocks: NFI required clocks. -- clock-names: NFI clocks internal name. -- ecc-engine: Required ECC Engine node. -- #address-cells: NAND chip index, should be 1. -- #size-cells: Should be 0. - -Example: - - nandc: nfi@1100d000 { - compatible =3D "mediatek,mt2701-nfc"; - reg =3D <0 0x1100d000 0 0x1000>; - interrupts =3D ; - clocks =3D <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names =3D "nfi_clk", "pad_clk"; - ecc-engine =3D <&bch>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - -Platform related properties, should be set in {platform_name}.dts: -- children nodes: NAND chips. - -Children nodes properties: -- reg: Chip Select Signal, default 0. - Set as reg =3D <0>, <1> when need 2 CS. -Optional: -- nand-on-flash-bbt: Store BBT on NAND Flash. -- nand-ecc-mode: the NAND ecc mode (check driver for supported modes) -- nand-ecc-step-size: Number of data bytes covered by a single ECC step. - valid values: - 512 and 1024 on mt2701 and mt2712. - 512 only on mt7622. - 1024 is recommended for large page NANDs. -- nand-ecc-strength: Number of bits to correct per ECC step. - The valid values that each controller supports: - mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60. - mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80. - mt7622: 4, 6, 8, 10, 12, 14, 16. - The strength should be calculated as follows: - E =3D (S - F) * 8 / B - S =3D O / (P / Q) - E : nand-ecc-strength. - S : spare size per sector. - F : FDM size, should be in the range [1,8]. - It is used to store free oob data. - O : oob size. - P : page size. - Q : nand-ecc-step-size. - B : number of parity bits needed to correct - 1 bitflip. - According to MTK NAND controller design, - this number depends on max ecc step size - that MTK NAND controller supports. - If max ecc step size supported is 1024, - then it should be always 14. And if max - ecc step size is 512, then it should be - always 13. - If the result does not match any one of the listed - choices above, please select the smaller valid value from - the list. - (otherwise the driver will do the adjustment at runtime) -- pinctrl-names: Default NAND pin GPIO setting name. -- pinctrl-0: GPIO setting node. - -Example: - &pio { - nand_pins_default: nanddefault { - pins_dat { - pinmux =3D , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength =3D ; - bias-pull-up; - }; - - pins_we { - pinmux =3D ; - drive-strength =3D ; - bias-pull-up =3D ; - }; - - pins_ale { - pinmux =3D ; - drive-strength =3D ; - bias-pull-down =3D ; - }; - }; - }; - - &nandc { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&nand_pins_default>; - nand@0 { - reg =3D <0>; - nand-on-flash-bbt; - nand-ecc-mode =3D "hw"; - nand-ecc-strength =3D <24>; - nand-ecc-step-size =3D <1024>; - }; - }; - -NAND chip optional subnodes: -- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml - -Example: - nand@0 { - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - preloader@0 { - label =3D "pl"; - read-only; - reg =3D <0x00000000 0x00400000>; - }; - android@00400000 { - label =3D "android"; - reg =3D <0x00400000 0x12c00000>; - }; - }; - }; - -2) ECC Engine: -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -Required BCH properties: -- compatible: Should be one of - "mediatek,mt2701-ecc", - "mediatek,mt2712-ecc", - "mediatek,mt7622-ecc". -- reg: Base physical address and size of ECC. -- interrupts: Interrupts of ECC. -- clocks: ECC required clocks. -- clock-names: ECC clocks internal name. - -Example: - - bch: ecc@1100e000 { - compatible =3D "mediatek,mt2701-ecc"; - reg =3D <0 0x1100e000 0 0x1000>; - interrupts =3D ; - clocks =3D <&pericfg CLK_PERI_NFI_ECC>; - clock-names =3D "nfiecc_clk"; - }; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index b8eba3ba153c..049ed797766b 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -360,7 +360,7 @@ thermal: thermal@1100b000 { mediatek,apmixedsys =3D <&apmixedsys>; }; =20 - nandc: nfi@1100d000 { + nandc: nand-controller@1100d000 { compatible =3D "mediatek,mt2701-nfc"; reg =3D <0 0x1100d000 0 0x1000>; interrupts =3D ; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dt= s/mediatek/mt2712e.dtsi index 92212cddd37e..cfbec2a2ed9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -560,7 +560,7 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 - nandc: nfi@1100e000 { + nandc: nand-controller@1100e000 { compatible =3D "mediatek,mt2712-nfc"; reg =3D <0 0x1100e000 0 0x1000>; interrupts =3D ; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts= /mediatek/mt7622.dtsi index 146e18b5b1f4..d98aa4936092 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -539,7 +539,7 @@ bluetooth { }; }; =20 - nandc: nfi@1100d000 { + nandc: nand-controller@1100d000 { compatible =3D "mediatek,mt7622-nfc"; reg =3D <0 0x1100D000 0 0x1000>; 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Mon, 05 Dec 2022 14:58:19 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:18 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:17 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 9/9] dt-bindings: mtd: ecc-mtk: Add compatible for MT7986 Date: Mon, 5 Dec 2022 14:57:56 +0800 Message-ID: <20221205065756.26875-10-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt-bindings documentation of ECC for MediaTek MT7986 SoC platform. Signed-off-by: Xiangsheng Hou --- .../devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine= .yaml b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml index b13d801eda76..505baf1e8830 100644 --- a/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml +++ b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml @@ -18,6 +18,7 @@ properties: - mediatek,mt2701-ecc - mediatek,mt2712-ecc - mediatek,mt7622-ecc + - mediatek,mt7986-ecc =20 reg: items: --=20 2.25.1