From nobody Thu Sep 18 17:20:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5A8AC47090 for ; Sat, 3 Dec 2022 07:42:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231326AbiLCHmS (ORCPT ); Sat, 3 Dec 2022 02:42:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229537AbiLCHmP (ORCPT ); Sat, 3 Dec 2022 02:42:15 -0500 Received: from mail-m121145.qiye.163.com (mail-m121145.qiye.163.com [115.236.121.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD62013EA5; Fri, 2 Dec 2022 23:42:11 -0800 (PST) Received: from amadeus-VLT-WX0.lan (unknown [218.85.118.194]) by mail-m121145.qiye.163.com (Hmail) with ESMTPA id 16184800087; Sat, 3 Dec 2022 15:42:08 +0800 (CST) From: Chukun Pan To: heiko@sntech.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chukun Pan , Krzysztof Kozlowski Subject: [PATCH v2 1/2] dt-bindings: arm: rockchip: Add Orange Pi R1 Plus Date: Sat, 3 Dec 2022 15:41:48 +0800 Message-Id: <20221203074149.11543-2-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221203074149.11543-1-amadeus@jmu.edu.cn> References: <20221203074149.11543-1-amadeus@jmu.edu.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZTE0fVh4ZGEpNHkodHR1DGlUTARMWGhIXJBQOD1 lXWRgSC1lBWUlKQ1VDTlVKSkNVSkJPWVdZFhoPEhUdFFlBWU9LSFVKSktISkNVSktLVUtZBg++ X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pk06Czo*MD0YCgpDVjYiAyER FRNPCxZVSlVKTUxLS05ISElDTE1IVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUlK Q1VDTlVKSkNVSkJPWVdZCAFZQUlJSEM3Bg++ X-HM-Tid: 0a84d6ef75a2b03akuuu16184800087 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add devicetree binding documentation for the Orange Pi R1 Plus. Signed-off-by: Chukun Pan Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 88ff4422a8c1..666a24992f88 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -761,6 +761,11 @@ properties: - const: tronsmart,orion-r68-meta - const: rockchip,rk3368 =20 + - description: Xunlong Orange Pi R1 Plus + items: + - const: xunlong,orangepi-r1-plus + - const: rockchip,rk3328 + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 --=20 2.25.1 From nobody Thu Sep 18 17:20:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A0F0C4332F for ; Sat, 3 Dec 2022 07:42:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231446AbiLCHmU (ORCPT ); Sat, 3 Dec 2022 02:42:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230315AbiLCHmP (ORCPT ); Sat, 3 Dec 2022 02:42:15 -0500 Received: from mail-m121145.qiye.163.com (mail-m121145.qiye.163.com [115.236.121.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2722D1570E; Fri, 2 Dec 2022 23:42:11 -0800 (PST) Received: from amadeus-VLT-WX0.lan (unknown [218.85.118.194]) by mail-m121145.qiye.163.com (Hmail) with ESMTPA id C93C98000B0; Sat, 3 Dec 2022 15:42:08 +0800 (CST) From: Chukun Pan To: heiko@sntech.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chukun Pan Subject: [PATCH v2 2/2] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus Date: Sat, 3 Dec 2022 15:41:49 +0800 Message-Id: <20221203074149.11543-3-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221203074149.11543-1-amadeus@jmu.edu.cn> References: <20221203074149.11543-1-amadeus@jmu.edu.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDT0NOVh4dSh5MSEIZHktNGlUTARMWGhIXJBQOD1 lXWRgSC1lBWUlKQ1VDTlVKSkNVSkJPWVdZFhoPEhUdFFlBWU9LSFVKSktISkNVSktLVUtZBg++ X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NDI6OSo6LT0eOAo4PStRAx8z C0swCipVSlVKTUxLS05ISElCT0JLVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUlK Q1VDTlVKSkNVSkJPWVdZCAFZQUpLTE5ONwY+ X-HM-Tid: 0a84d6ef786cb03akuuuc93c98000b0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. This device is similar to the NanoPi R2S, and has a 16MB SPI NOR (mx25l12805d). The reset button is changed to directly reset the power supply, another detail is that both network ports have independent MAC addresses. Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++ 2 files changed, 374 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 0a76a2ebb5f6..27e00f4f3c86 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3326-odroid-go3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3328-nanopi-r2s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3328-orangepi-r1-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3328-rock-pi-e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3328-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts b/arc= h/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts new file mode 100644 index 000000000000..dc83d74045a3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Based on rk3328-nanopi-r2s.dts, which is: + * Copyright (c) 2020 David Bauer + */ + +/dts-v1/; + +#include +#include +#include "rk3328.dtsi" + +/ { + model =3D "Xunlong Orange Pi R1 Plus"; + compatible =3D "xunlong,orangepi-r1-plus", "rockchip,rk3328"; + + aliases { + ethernet1 =3D &rtl8153; + mmc0 =3D &sdmmc; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + gmac_clk: gmac-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + clock-output-names =3D "gmac_clkin"; + #clock-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-0 =3D <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names =3D "default"; + + led-0 { + function =3D LED_FUNCTION_LAN; + color =3D ; + gpios =3D <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + led-2 { + function =3D LED_FUNCTION_WAN; + color =3D ; + gpios =3D <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc_sd: sdmmc-regulator { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&sdmmc0m1_pin>; + pinctrl-names =3D "default"; + regulator-name =3D "vcc_sd"; + regulator-boot-on; + vin-supply =3D <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vdd_5v_lan: vdd-5v-lan-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&lan_vdd_pin>; + pinctrl-names =3D "default"; + regulator-name =3D "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc_sys>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&display_subsystem { + status =3D "disabled"; +}; + +&gmac2io { + assigned-clocks =3D <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents =3D <&gmac_clk>, <&gmac_clk>; + clock_in_out =3D "input"; + phy-handle =3D <&rtl8211e>; + phy-mode =3D "rgmii"; + phy-supply =3D <&vcc_io>; + pinctrl-0 =3D <&rgmiim1_pins>; + pinctrl-names =3D "default"; + snps,aal; + rx_delay =3D <0x18>; + tx_delay =3D <0x24>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + rtl8211e: ethernet-phy@1 { + reg =3D <1>; + pinctrl-0 =3D <ð_phy_reset_pin>; + pinctrl-names =3D "default"; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <50000>; + reset-gpios =3D <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status =3D "okay"; + + rk805: pmic@18 { + compatible =3D "rockchip,rk805"; + reg =3D <0x18>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells =3D <1>; + clock-output-names =3D "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-0 =3D <&pmic_int_l>; + pinctrl-names =3D "default"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply =3D <&vcc_sys>; + vcc2-supply =3D <&vcc_sys>; + vcc3-supply =3D <&vcc_sys>; + vcc4-supply =3D <&vcc_sys>; + vcc5-supply =3D <&vcc_io>; + vcc6-supply =3D <&vcc_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <712500>; + regulator-max-microvolt =3D <1450000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name =3D "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <712500>; + regulator-max-microvolt =3D <1450000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name =3D "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name =3D "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name =3D "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name =3D "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + pmuio-supply =3D <&vcc_io>; + vccio1-supply =3D <&vcc_io>; + vccio2-supply =3D <&vcc18_emmc>; + vccio3-supply =3D <&vcc_io>; + vccio4-supply =3D <&vcc_io>; + vccio5-supply =3D <&vcc_io>; + vccio6-supply =3D <&vcc_io>; + status =3D "okay"; +}; + +&pinctrl { + gmac2io { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins =3D <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + lan_led_pin: lan-led-pin { + rockchip,pins =3D <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins =3D <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins =3D <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lan { + lan_vdd_pin: lan-vdd-pin { + rockchip,pins =3D <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins =3D <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-0 =3D <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus= 4>; + pinctrl-names =3D "default"; + vmmc-supply =3D <&vcc_sd>; + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <0>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; +}; + +&u2phy_host { + status =3D "okay"; +}; + +&u2phy_otg { + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&usb20_otg { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbdrd3 { + dr_mode =3D "host"; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible =3D "usbbda,8153"; + reg =3D <2>; + }; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; --=20 2.25.1