From nobody Thu Sep 18 18:52:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04A6AC352A1 for ; Sat, 3 Dec 2022 06:47:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230247AbiLCGrq (ORCPT ); Sat, 3 Dec 2022 01:47:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231537AbiLCGr3 (ORCPT ); Sat, 3 Dec 2022 01:47:29 -0500 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADC1FDBF64 for ; Fri, 2 Dec 2022 22:47:20 -0800 (PST) Received: by mail-pg1-x531.google.com with SMTP id 136so6148557pga.1 for ; Fri, 02 Dec 2022 22:47:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PXYoHLXQCavco5NNh0sXuOKKVYR0blfrb+/AP/qt1J8=; b=SRWO1OIPm7D9r5xdKjxp4xaECGXNSkdwStSz7PxxiJv4HkPwAgC9enbPktE2nZfVaS FJ4cXx3XVG3XBnKbigJUdvitSNRYo5L5I3eUCtUJIgfTp08sbQTixF1PXo8b7D7PEdLb iH784Sx+3URzIDr4BkLiPAANGDipXV/4FgE0ST5P7cTV4L7FQ7AyCogSsZqm5QTt5Zd8 wH5XRe02PWbkHp1m8dR42LGXNYTaZO/Z8/ssxRGtMGukZJ+hMuuswbOGK/a3Bu60srED m+KW2sQ3Y2NozzTmpUA2UKGbvkviHok4vDvh7VJyJzBvu16Qy2STc2DB75IsQMsJNJSC EKNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PXYoHLXQCavco5NNh0sXuOKKVYR0blfrb+/AP/qt1J8=; b=5X1mcNqEIwv3snqMAtUxS5xjaraVKQRJgSQVoycd3I29c8aWkxDXZFtXvVtOZ0LEJK oV/zesgaVcIHHbn4jQMOv0D3mQfk5avFp1cBqMZ2/CId/jNbsln6KiPRnTVrYVyLILHq mhkfgu5qXJzy+BWW5muyBLZuo/3EH4mArcNKYg82ypVAj6euZlAeR5iTX91gHF/fJcaZ H77UfhetPp9ayQCf5fxN0XmGHMkjxxaYeBJxsnTYml0o55CUMaYEMun+cUWgjNM5WS0e G/pQ9O47PD364FlD6sq4QO8fAf8/NKW9DEyaURbgmd4971iLKhg+XwwACXm/LkOCnV6s WSoA== X-Gm-Message-State: ANoB5pmqHklYP6P2MXjmTNQ2aS2jV6v8ECZS+j3IbWC75FuNfcm5Fk3f 9QgzW9Ql+IZNSpXmrb0DKMI3Ww== X-Google-Smtp-Source: AA0mqf6w60bkdL+GArK2RcsmZfct++Y+KVRtsmVscRai6QBVbF8LDWExSXNuXk2SPGv79T41xUdhNw== X-Received: by 2002:a63:1920:0:b0:478:7e03:1ffe with SMTP id z32-20020a631920000000b004787e031ffemr7834501pgl.209.1670050040099; Fri, 02 Dec 2022 22:47:20 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id t17-20020aa79471000000b00575c8242849sm6102091pfq.69.2022.12.02.22.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 22:47:19 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Hector Martin , Sven Peter , Alyssa Rosenzweig , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, Anup Patel , Atish Patra Subject: [PATCH v15 6/9] RISC-V: Use IPIs for remote TLB flush when possible Date: Sat, 3 Dec 2022 12:16:26 +0530 Message-Id: <20221203064629.1601299-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221203064629.1601299-1-apatel@ventanamicro.com> References: <20221203064629.1601299-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote TLB flushes directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote TLB flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 37ed760d007c..27a7db8eb2c4 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -23,14 +23,62 @@ static inline void local_flush_tlb_page_asid(unsigned l= ong addr, : "memory"); } =20 +static inline void local_flush_tlb_range(unsigned long start, + unsigned long size, unsigned long stride) +{ + if (size <=3D stride) + local_flush_tlb_page(start); + else + local_flush_tlb_all(); +} + +static inline void local_flush_tlb_range_asid(unsigned long start, + unsigned long size, unsigned long stride, unsigned long asid) +{ + if (size <=3D stride) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_all_asid(asid); +} + +static void __ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (riscv_use_ipi_for_rfence()) + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); + else + sbi_remote_sfence_vma(NULL, 0, -1); +} + +struct flush_tlb_range_data { + unsigned long asid; + unsigned long start; + unsigned long size; + unsigned long stride; +}; + +static void __ipi_flush_tlb_range_asid(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); +} + +static void __ipi_flush_tlb_range(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range(d->start, d->size, d->stride); } =20 -static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long star= t, - unsigned long size, unsigned long stride) +static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct flush_tlb_range_data ftd; struct cpumask *cmask =3D mm_cpumask(mm); unsigned int cpuid; bool broadcast; @@ -45,19 +93,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm,= unsigned long start, unsigned long asid =3D atomic_long_read(&mm->context.id); =20 if (broadcast) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); - } else if (size <=3D stride) { - local_flush_tlb_page_asid(start, asid); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D asid; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range_asid, + &ftd, 1); + } else + sbi_remote_sfence_vma_asid(cmask, + start, size, asid); } else { - local_flush_tlb_all_asid(asid); + local_flush_tlb_range_asid(start, size, stride, asid); } } else { if (broadcast) { - sbi_remote_sfence_vma(cmask, start, size); - } else if (size <=3D stride) { - local_flush_tlb_page(start); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D 0; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range, + &ftd, 1); + } else + sbi_remote_sfence_vma(cmask, start, size); } else { - local_flush_tlb_all(); + local_flush_tlb_range(start, size, stride); } } =20 @@ -66,23 +129,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm= , unsigned long start, =20 void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } =20 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } =20 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif --=20 2.34.1