From nobody Thu Sep 18 18:52:38 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA38DC4332F for ; Sat, 3 Dec 2022 06:47:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231709AbiLCGrm (ORCPT ); Sat, 3 Dec 2022 01:47:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231611AbiLCGrY (ORCPT ); Sat, 3 Dec 2022 01:47:24 -0500 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18347D78D0 for ; Fri, 2 Dec 2022 22:47:14 -0800 (PST) Received: by mail-pg1-x52c.google.com with SMTP id f3so6144386pgc.2 for ; Fri, 02 Dec 2022 22:47:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l859abxuoE/VhU1BOMI96Rzc7qDQ9lMT8rygPSRaCPw=; b=bs3ldEY1b6Xgz4sLz6S1EL4dqYso6cHOZqnCj5m+HYQkFd25ZV6+oys4SwswX8oTDw Sqxfj3yyeGEGKm8g4Y9aJRg1iq53w5hyxgpOdyJlAzwKo9s/ejUYBd2LYirRkHJMeGKW 5R4tF7pnET2SV1yKdZD6zlGtEGISxZNB1r6uuLOrdBs9UomRitHeanMszt3c2Aq9ABYv SwW8lIYHtG/zyKO8prYaAycBHjnn/h4VGsPypRRjuTDyeQ2Vu7V8HwTRavddkjHKBgJW BBXZi1DuW5HKs+f0LNbOZZIrBTEB04n8OwcwHet9jbE87SKvCAiZI9WjZ0TG5bTYeHDJ VQwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l859abxuoE/VhU1BOMI96Rzc7qDQ9lMT8rygPSRaCPw=; b=B+bOwoIrhdTmCVvR5MyYgbMSKFwuX26DiuBZHfSAXfHrKhgbyESc9BvF1kcVKYZ/WE AWNtQg1Uhksov5L2h/KFOIfFxZYL28mTdx3iXg2k+DNm5dcuGeK8h7C3A+ynH2KqulYo Q+TEykN5EQrr/B8HchoQ0RznbF2qRd3Abup16NQdUFTvQyZS6B9AkF9zgCLcClW1Zvfu 2Kh0XzkoL04CJGXkKpSYvOHVKhxMC/pDwD0jg8ucgunRgDXT7bV5+rE1Ga8oyzFy0Exp XAwmEoivhsXP8FddvxWkcr8P0Cd1/Vdc7v5XZV9JBEbR+SjVynU++SikFOWbtY56sBox gUtQ== X-Gm-Message-State: ANoB5pngNWl6qKoSq9xApC9W2KWOQlLwRhyFiTqb4S+wF72utjOWN0Rb tw/7tYOdb8UoA7y4+10jBjP8yg== X-Google-Smtp-Source: AA0mqf5yd+LbMSCDmq4XSkVV5tr8UCBC7QyEn1v4kmnuty5zX48XBQGBOViFcTcPyylBQ5GI5rVobg== X-Received: by 2002:a63:2d44:0:b0:46f:7e1c:2bb7 with SMTP id t65-20020a632d44000000b0046f7e1c2bb7mr49464121pgt.368.1670050034240; Fri, 02 Dec 2022 22:47:14 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id t17-20020aa79471000000b00575c8242849sm6102091pfq.69.2022.12.02.22.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 22:47:13 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Hector Martin , Sven Peter , Alyssa Rosenzweig , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, Anup Patel , Atish Patra Subject: [PATCH v15 5/9] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Sat, 3 Dec 2022 12:16:25 +0530 Message-Id: <20221203064629.1601299-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221203064629.1601299-1-apatel@ventanamicro.com> References: <20221203064629.1601299-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the supervisor mode (i.e. RISC-V kernel) instead of using SBI calls. The upcoming AIA IMSIC devices allow direct IPI injection from the supervisor mode (i.e. RISC-V kernel). To support this, we extend the riscv_ipi_set_virq_range() function so that IPI provider (i.e. irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/sbi-ipi.c | 2 +- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 79ed0b73cd4e..56976e41a21e 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); =20 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr); +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -93,10 +101,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } =20 -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } =20 +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ =20 #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c index 41981ab88493..a4559695ce62 100644 --- a/arch/riscv/kernel/sbi-ipi.c +++ b/arch/riscv/kernel/sbi-ipi.c @@ -72,6 +72,6 @@ void __init sbi_ipi_init(void) "irqchip/sbi-ipi:starting", sbi_ipi_starting_cpu, NULL); =20 - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, false); pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index e8a20454d65b..74b8cb1a89ab 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -145,7 +145,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } =20 -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; =20 @@ -168,6 +171,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) =20 /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 7ccc16dd6a76..9a55e733ae99 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -251,7 +251,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) } =20 irq_set_chained_handler(clint_ipi_irq, clint_ipi_interrupt); - riscv_ipi_set_virq_range(rc, BITS_PER_BYTE); + riscv_ipi_set_virq_range(rc, BITS_PER_BYTE, true); clint_clear_ipi(); #endif =20 --=20 2.34.1