From nobody Thu Sep 18 20:20:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ACB8C47088 for ; Fri, 2 Dec 2022 16:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233885AbiLBQGQ (ORCPT ); Fri, 2 Dec 2022 11:06:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233762AbiLBQGJ (ORCPT ); Fri, 2 Dec 2022 11:06:09 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2869F8AADE; Fri, 2 Dec 2022 08:05:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669997159; x=1701533159; h=from:to:subject:date:message-id:in-reply-to:references: mime-version; bh=c9PfDjNuPB6YaUdPal786fGIVEEfoGwJh+78D3mIp2k=; b=ZOav4ixfGlPD5nILboRc7/EDAFQJ+oB02YBWR+cEGoTS/poaruOrLJmp FWm85L7ncHUEMgZ8v7gKD1CoEAMelfcddSSFrUWitWXVTZrp3moC/uRAu dDY6R7bHdL4UuCwvx21CaoeX51OwIabOGUpLSB5xPjchLEOHp/aXasCn9 S1piF2Kag+utEEXiXvhpJyPqT/IupjC4SLv35njxPzOEAm3T2HBpIcf1g kdd5SgYPSO5tvilcLPP/MBQmd7m6XiwMW2bOdf9oJyFssavjITxo0ijZQ cpw/NL7S3XPGIXagtcYVoP2RtciATUUD+Y+7jze2WaguqKrC6C81zmQ4T w==; X-IronPort-AV: E=Sophos;i="5.96,212,1665471600"; d="scan'208";a="189775667" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Dec 2022 09:05:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 2 Dec 2022 09:05:33 -0700 Received: from AUS-LT-C33025.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 2 Dec 2022 09:05:32 -0700 From: Jerry Ray To: Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , , , Jerry Ray Subject: [PATCH net-next 2/2] dsa: lan9303: Move to PHYLINK Date: Fri, 2 Dec 2022 10:05:29 -0600 Message-ID: <20221202160529.30010-3-jerry.ray@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221202160529.30010-1-jerry.ray@microchip.com> References: <20221202160529.30010-1-jerry.ray@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch replaces the .adjust_link api with the .phylink_get_caps api. Signed-off-by: Jerry Ray --- drivers/net/dsa/lan9303-core.c | 73 +++++++++++++++++----------------- 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/lan9303-core.c b/drivers/net/dsa/lan9303-core.c index ed8f83f3a654..b9b3f1b69063 100644 --- a/drivers/net/dsa/lan9303-core.c +++ b/drivers/net/dsa/lan9303-core.c @@ -1096,42 +1096,6 @@ static int lan9303_phy_write(struct dsa_switch *ds, = int phy, int regnum, return chip->ops->phy_write(chip, phy, regnum, val); } =20 -static void lan9303_adjust_link(struct dsa_switch *ds, int port, - struct phy_device *phydev) -{ - struct lan9303 *chip =3D ds->priv; - int ctl; - - if (!phy_is_pseudo_fixed_link(phydev)) - return; - - ctl =3D lan9303_phy_read(ds, port, MII_BMCR); - - ctl &=3D ~BMCR_ANENABLE; - - if (phydev->speed =3D=3D SPEED_100) - ctl |=3D BMCR_SPEED100; - else if (phydev->speed =3D=3D SPEED_10) - ctl &=3D ~BMCR_SPEED100; - else - dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed); - - if (phydev->duplex =3D=3D DUPLEX_FULL) - ctl |=3D BMCR_FULLDPLX; - else - ctl &=3D ~BMCR_FULLDPLX; - - lan9303_phy_write(ds, port, MII_BMCR, ctl); - - if (port =3D=3D chip->phy_addr_base) { - /* Virtual Phy: Remove Turbo 200Mbit mode */ - lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl); - - ctl &=3D ~LAN9303_VIRT_SPECIAL_TURBO; - regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ctl); - } -} - static int lan9303_port_enable(struct dsa_switch *ds, int port, struct phy_device *phy) { @@ -1328,6 +1292,41 @@ static int lan9303_port_mdb_del(struct dsa_switch *d= s, int port, return 0; } =20 +static void lan9303_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + struct lan9303 *chip =3D ds->priv; + + dev_dbg(chip->dev, "%s(%d) entered.", __func__, port); + + config->mac_capabilities =3D MAC_10 | MAC_100 | MAC_ASYM_PAUSE | + MAC_SYM_PAUSE; + + if (dsa_port_is_cpu(dsa_to_port(ds, port))) { + /* cpu port */ + phy_interface_empty(config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_RMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_MII, + config->supported_interfaces); + } else { + /* internal ports */ + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + /* Compatibility for phylib's default interface type when the + * phy-mode property is absent + */ + __set_bit(PHY_INTERFACE_MODE_GMII, + config->supported_interfaces); + } + + /* This driver does not make use of the speed, duplex, pause or the + * advertisement in its mac_config, so it is safe to mark this driver + * as non-legacy. + */ + config->legacy_pre_march2020 =3D false; +} + /* For non-cpu ports, the max frame size is 1518. * The CPU port supports a max frame size of 1522. * There is a JUMBO flag to make the max size 2048, but this driver @@ -1353,7 +1352,7 @@ static const struct dsa_switch_ops lan9303_switch_ops= =3D { .get_strings =3D lan9303_get_strings, .phy_read =3D lan9303_phy_read, .phy_write =3D lan9303_phy_write, - .adjust_link =3D lan9303_adjust_link, + .phylink_get_caps =3D lan9303_phylink_get_caps, .get_ethtool_stats =3D lan9303_get_ethtool_stats, .get_sset_count =3D lan9303_get_sset_count, .port_enable =3D lan9303_port_enable, --=20 2.17.1