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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id l16-20020ac24310000000b00498f871f33fsm1043273lfh.86.2022.12.02.07.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 07:21:02 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Srinivas Kandagatla , Krzysztof Kozlowski Subject: [PATCH v6 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS Date: Fri, 2 Dec 2022 16:20:53 +0100 Message-Id: <20221202152054.357316-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202152054.357316-1-krzysztof.kozlowski@linaro.org> References: <20221202152054.357316-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Srinivas Kandagatla Add Soundwire controllers, Low Power Audio SubSystem (LPASS) devices and LPASS pin controller. Signed-off-by: Srinivas Kandagatla Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v5: 1. Use different clocks (codec@31e0000, codec@3240000). 2. Order LPASS pinctrl nodes by GPIO number. 3. Add dmic01-default-state and dmic02-default-state to LPASS pinctrl. Changes since v4: 1. Re-order few properties between Soundwire nodes, to keep them ordered consistently. 2. Drop unsupported qcom,port-offset. Changes since v3: 1. Re-order reg and sound-dai-cells. Changes since v2: 1. Use lower-case hex. Changes since v1: 1. Whitespace cleanups. 2. Correct include - do not use deprecated one. --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 324 +++++++++++++++++++++++++++ 1 file changed, 324 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 7b63c56ff2f4..acc73caa056f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 / { @@ -2090,6 +2091,209 @@ compute-cb@3 { }; }; =20 + wsa2macro: codec@31e0000 { + compatible =3D "qcom,sm8450-lpass-wsa-macro"; + reg =3D <0 0x031e0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE= _COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPL= E_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_A= TTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wsa2_swr_active>; + #sound-dai-cells =3D <1>; + }; + + /* WSA2 */ + swr4: soundwire-controller@31f0000 { + compatible =3D "qcom,soundwire-v1.7.0"; + reg =3D <0 0x031f0000 0 0x2000>; + interrupts =3D ; + clocks =3D <&wsa2macro>; + clock-names =3D "iface"; + + qcom,din-ports =3D <2>; + qcom,dout-ports =3D <6>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x= 0f 0x0f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x= 0a>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x= 00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xf= f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff= >; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff= 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 = 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + }; + + rxmacro: codec@3200000 { + compatible =3D "qcom,sm8450-lpass-rx-macro"; + reg =3D <0 0x3200000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_AT= TRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_CO= UPLE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rx_swr_active>; + #sound-dai-cells =3D <1>; + }; + + swr1: soundwire-controller@3210000 { + compatible =3D "qcom,soundwire-v1.7.0"; + reg =3D <0 0x3210000 0 0x2000>; + interrupts =3D ; + clocks =3D <&rxmacro>; + clock-names =3D "iface"; + label =3D "RX"; + qcom,din-ports =3D <0>; + qcom,dout-ports =3D <5>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + }; + + txmacro: codec@3220000 { + compatible =3D "qcom,sm8450-lpass-tx-macro"; + reg =3D <0 0x3220000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_C= OUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_AT= TRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_CO= UPLE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tx_swr_active>; + #sound-dai-cells =3D <1>; + }; + + wsamacro: codec@3240000 { + compatible =3D "qcom,sm8450-lpass-wsa-macro"; + reg =3D <0 0x03240000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE= _NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names =3D "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_A= TTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>; + assigned-clock-rates =3D <19200000>, <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wsa_swr_active>; + #sound-dai-cells =3D <1>; + }; + + /* WSA */ + swr0: soundwire-controller@3250000 { + compatible =3D "qcom,soundwire-v1.7.0"; + reg =3D <0 0x03250000 0 0x2000>; + interrupts =3D ; + clocks =3D <&wsamacro>; + clock-names =3D "iface"; + + qcom,din-ports =3D <2>; + qcom,dout-ports =3D <6>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x= 0f 0x0f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x= 0a>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x= 00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xf= f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff= >; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff= 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 = 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + }; + + swr2: soundwire-controller@33b0000 { + compatible =3D "qcom,soundwire-v1.7.0"; + reg =3D <0 0x33b0000 0 0x2000>; + interrupts-extended =3D <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "core", "wake"; + + clocks =3D <&vamacro>; + clock-names =3D "iface"; + label =3D "TX"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <0>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + }; + + vamacro: codec@33f0000 { + compatible =3D "qcom,sm8450-lpass-va-macro"; + reg =3D <0 0x033f0000 0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>; + clock-names =3D "mclk", "macro", "dcodec", "npl"; + assigned-clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRI= BUTE_COUPLE_NO>; + assigned-clock-rates =3D <19200000>; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + remoteproc_adsp: remoteproc@30000000 { compatible =3D "qcom,sm8450-adsp-pas"; reg =3D <0 0x30000000 0 0x100>; @@ -3023,6 +3227,123 @@ qup_uart20_default: qup-uart20-default-state { =20 }; =20 + lpass_tlmm: pinctrl@3440000{ + compatible =3D "qcom,sm8450-lpass-lpi-pinctrl"; + reg =3D <0 0x3440000 0x0 0x20000>, + <0 0x34d0000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic02_default: dmic02-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sm8450-smmu-500", "arm,mmu-500"; reg =3D <0 0x15000000 0 0x100000>; @@ -3501,6 +3822,9 @@ lpass_ag_noc: interconnect@3c40000 { }; }; =20 + sound: sound { + }; + thermal-zones { aoss0-thermal { polling-delay-passive =3D <0>; --=20 2.34.1