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This helps in maintaining the uniformity across all of the QMP PHY drivers. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 146 ++++++++++++------------ 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 318eea35b972..20fcdbef8c77 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -94,7 +94,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_= LAYOUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -143,12 +143,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -162,7 +162,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl= [] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -218,12 +218,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), @@ -241,7 +241,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f), @@ -253,7 +253,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), @@ -295,13 +295,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -320,7 +320,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -331,7 +331,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -361,7 +361,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -370,7 +370,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -408,7 +408,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_t= bl[] =3D { =20 }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -418,7 +418,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -448,7 +448,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -460,7 +460,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -500,7 +500,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -632,12 +632,12 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes_tbl), - .tx_tbl =3D msm8996_ufs_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx_tbl), - .rx_tbl =3D msm8996_ufs_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx_tbl), + .serdes_tbl =3D msm8996_ufs_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), + .tx_tbl =3D msm8996_ufs_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), + .rx_tbl =3D msm8996_ufs_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -655,14 +655,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -673,14 +673,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), - .tx_tbl =3D sdm845_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx_tbl), - .rx_tbl =3D sdm845_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx_tbl), - .pcs_tbl =3D sdm845_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), + .serdes_tbl =3D sdm845_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx_tbl =3D sdm845_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx_tbl =3D sdm845_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs_tbl =3D sdm845_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -693,14 +693,14 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), - .tx_tbl =3D sm6115_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx_tbl), - .rx_tbl =3D sm6115_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx_tbl), - .pcs_tbl =3D sm6115_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), + .serdes_tbl =3D sm6115_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx_tbl =3D sm6115_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx_tbl =3D sm6115_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs_tbl =3D sm6115_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -713,14 +713,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), - .tx_tbl =3D sm8150_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx_tbl), - .rx_tbl =3D sm8150_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx_tbl), - .pcs_tbl =3D sm8150_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8150_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx_tbl =3D sm8150_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx_tbl =3D sm8150_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs_tbl =3D sm8150_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -731,14 +731,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -749,14 +749,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69FA9C4321E for ; Thu, 1 Dec 2022 17:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbiLARoJ (ORCPT ); Thu, 1 Dec 2022 12:44:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230192AbiLARoB (ORCPT ); Thu, 1 Dec 2022 12:44:01 -0500 Received: from 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([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:43:54 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 02/23] phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions Date: Thu, 1 Dec 2022 23:13:07 +0530 Message-Id: <20221201174328.870152-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 20fcdbef8c77..35b77cd79e57 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -94,7 +94,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_= LAYOUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -143,12 +143,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -629,15 +629,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { .rx2 =3D 0xa00, }; =20 -static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { +static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), - .tx_tbl =3D msm8996_ufs_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), - .rx_tbl =3D msm8996_ufs_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), + .serdes_tbl =3D msm8996_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx_tbl =3D msm8996_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx_tbl =3D msm8996_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -1156,7 +1156,7 @@ static int qmp_ufs_probe(struct platform_device *pdev) static const struct of_device_id qmp_ufs_of_match_table[] =3D { { .compatible =3D "qcom,msm8996-qmp-ufs-phy", - .data =3D &msm8996_ufs_cfg, + .data =3D &msm8996_ufsphy_cfg, }, { .compatible =3D "qcom,msm8998-qmp-ufs-phy", .data =3D &sdm845_ufsphy_cfg, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 550DAC47088 for ; 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Thu, 01 Dec 2022 09:44:01 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 03/23] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct Date: Thu, 1 Dec 2022 23:13:08 +0530 Message-Id: <20221201174328.870152-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 196 ++++++++++++++---------- 1 file changed, 113 insertions(+), 83 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 35b77cd79e57..516027e356f0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -527,21 +527,26 @@ struct qmp_ufs_offsets { u16 rx2; }; =20 +struct qmp_phy_cfg_tbls { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes; + int serdes_num; + const struct qmp_phy_init_tbl *tx; + int tx_num; + const struct qmp_phy_init_tbl *rx; + int rx_num; + const struct qmp_phy_init_tbl *pcs; + int pcs_num; +}; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { int lanes; =20 const struct qmp_ufs_offsets *offsets; =20 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_cfg_tbls tbls; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -632,12 +637,14 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), - .tx_tbl =3D msm8996_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), - .rx_tbl =3D msm8996_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + .tbls =3D { + .serdes =3D msm8996_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx =3D msm8996_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx =3D msm8996_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + }, =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -655,14 +662,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -673,14 +682,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), - .tx_tbl =3D sdm845_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), - .rx_tbl =3D sdm845_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), - .pcs_tbl =3D sdm845_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + .tbls =3D { + .serdes =3D sdm845_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx =3D sdm845_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx =3D sdm845_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs =3D sdm845_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -693,14 +704,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), - .tx_tbl =3D sm6115_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), - .rx_tbl =3D sm6115_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), - .pcs_tbl =3D sm6115_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm6115_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx =3D sm6115_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx =3D sm6115_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs =3D sm6115_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -713,14 +726,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), - .tx_tbl =3D sm8150_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), - .rx_tbl =3D sm8150_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), - .pcs_tbl =3D sm8150_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -731,14 +746,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -749,14 +766,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -790,16 +809,40 @@ static void qmp_ufs_configure(void __iomem *base, qmp_ufs_configure_lane(base, tbl, num, 0xff); } =20 -static int qmp_ufs_serdes_init(struct qmp_ufs *qmp) +static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_= cfg_tbls *tbls) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; void __iomem *serdes =3D qmp->serdes; - const struct qmp_phy_init_tbl *serdes_tbl =3D cfg->serdes_tbl; - int serdes_tbl_num =3D cfg->serdes_tbl_num; =20 - qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num); + qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num); +} =20 - return 0; +static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_c= fg_tbls *tbls) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + void __iomem *tx =3D qmp->tx; + void __iomem *rx =3D qmp->rx; + + qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1); + qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1); + + if (cfg->lanes >=3D 2) { + qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2); + qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2); + } +} + +static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg= _tbls *tbls) +{ + void __iomem *pcs =3D qmp->pcs; + + qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num); +} + +static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_p= hy_cfg *cfg) +{ + qmp_ufs_serdes_init(qmp, &cfg->tbls); + qmp_ufs_lanes_init(qmp, &cfg->tbls); + qmp_ufs_pcs_init(qmp, &cfg->tbls); } =20 static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -886,25 +929,12 @@ static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; - void __iomem *tx =3D qmp->tx; - void __iomem *rx =3D qmp->rx; void __iomem *pcs =3D qmp->pcs; void __iomem *status; unsigned int val; int ret; =20 - qmp_ufs_serdes_init(qmp); - - /* Tx, Rx, and PCS configurations */ - qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); - qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); - - if (cfg->lanes >=3D 2) { - qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); - qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); - } - - qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_ufs_init_registers(qmp, cfg); =20 ret =3D reset_control_deassert(qmp->ufs_reset); if (ret) --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88EF6C4321E for ; Thu, 1 Dec 2022 17:44:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229726AbiLARoc (ORCPT ); Thu, 1 Dec 2022 12:44:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230220AbiLARoM (ORCPT ); Thu, 1 Dec 2022 12:44:12 -0500 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52139B71CD for ; Thu, 1 Dec 2022 09:44:09 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id h33so2265247pgm.9 for ; Thu, 01 Dec 2022 09:44:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9mbDirqLKXr/5FgIX54AJCxh8nLq142NlZCiPSIMpPM=; b=sni+VE39ph4Wmu0pSL4SAxtRsH0USVCJEeh0Ru52p3PFG6T8aN2b62f8x+Jr3HDW8Z Rm7k+dqCqcvwqG8aN3CcVm7W8EjC3sLjebFHJWv4hMdDy/rqncSvSKCf8YolNNIC3oBu 4QPGEUjE4DyX3DKjfY5J4JaiD0wXub7mvBy1zlZ+x3Vvbow3lNGzbC+qxGJuvSWim41W Om84NnbGTEop+u7Is8zBg8KDji2uhDdiyPJ5yWgHtOacWRt+q/GLvTm0ddA2gs688Bm5 20dfDRKUvHN/AF3qq8atg9JOX73GN1l6GaVZvtHn8JPxqN+MPoOngeKV9SFphBuK1gJB x9Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9mbDirqLKXr/5FgIX54AJCxh8nLq142NlZCiPSIMpPM=; b=IU/cZEIAg0E8FW02dV2nMkROhIlg/0x2rWy3hUihjUUE9NzI01rce5YzkkPgG99gqb gfTk0eZQv/6CPQQXqw7ubXIK1Nqu+YBEQD3uki8tsDAgY2AkH4FKzaEqN1xo/j8U3LHJ ffqr8MrkvEa9cfvmGL/KHTw9swbA3953/7ZbU4he/Sh76CJe6MZeIQXL5dRwzSLENT4a RR4mrh/ivDx68RsQNmZh9lsV6RGJq39IwF3BTVF44Mh/F+sJ5Bv14m/Uj0liTLfN1JBq NVLRd3G0UlHKGZg0wXtfeQSHZfgIt5CEQHJSilsIaDFvOiZcjRwxdfM9S6Wo6csTa4wB RqOA== X-Gm-Message-State: ANoB5plskJ7cFXEdzyJCBKuQixKT/UbS0PPVP6K7gQRmjzVKH1iZC1/N 3ZThn8wgSSfIUfE3P3ZHPXaH X-Google-Smtp-Source: AA0mqf6tDTI+X3TwNGz54Kh+X1FOzooq89OmoICdtqmBjTnZWRiH7OBEycCI7N9VfWSUb485MxkmAA== X-Received: by 2002:aa7:8542:0:b0:575:3c6a:f05c with SMTP id y2-20020aa78542000000b005753c6af05cmr20007862pfn.25.1669916648890; Thu, 01 Dec 2022 09:44:08 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:44:08 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 04/23] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Date: Thu, 1 Dec 2022 23:13:09 +0530 Message-Id: <20221201174328.870152-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 516027e356f0..2d5dd336aeb2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -547,6 +547,8 @@ struct qmp_phy_cfg { =20 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tbls tbls; + /* Additional sequence for HS Series B */ + const struct qmp_phy_cfg_tbls tbls_hs_b; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -580,6 +582,7 @@ struct qmp_ufs { struct reset_control *ufs_reset; =20 struct phy *phy; + u32 mode; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -841,6 +844,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const= struct qmp_phy_cfg_tbls static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_p= hy_cfg *cfg) { qmp_ufs_serdes_init(qmp, &cfg->tbls); + if (qmp->mode =3D=3D PHY_MODE_UFS_HS_B) + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qmp, &cfg->tbls); qmp_ufs_pcs_init(qmp, &cfg->tbls); } @@ -1011,9 +1016,19 @@ static int qmp_ufs_disable(struct phy *phy) return qmp_ufs_exit(phy); } =20 +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submo= de) +{ + struct qmp_ufs *qmp =3D phy_get_drvdata(phy); + + qmp->mode =3D mode; + + return 0; +} + static const struct phy_ops qcom_qmp_ufs_phy_ops =3D { .power_on =3D qmp_ufs_enable, .power_off =3D qmp_ufs_disable, + .set_mode =3D qmp_ufs_set_mode, .owner =3D THIS_MODULE, }; =20 --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 671E6C47089 for ; Thu, 1 Dec 2022 17:44:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229823AbiLARoo (ORCPT ); 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Thu, 01 Dec 2022 09:44:15 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 05/23] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Date: Thu, 1 Dec 2022 23:13:10 +0530 Message-Id: <20221201174328.870152-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 2d5dd336aeb2..82be9b754e8e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -20,6 +20,7 @@ #include #include =20 +#include #include "phy-qcom-qmp.h" =20 /* QPHY_SW_RESET bit */ @@ -549,6 +550,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b; + /* Additional sequence for HS G4 */ + const struct qmp_phy_cfg_tbls tbls_hs_g4; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -583,6 +586,7 @@ struct qmp_ufs { =20 struct phy *phy; u32 mode; + u32 submode; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -847,7 +851,11 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp= , const struct qmp_phy_cfg if (qmp->mode =3D=3D PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qmp, &cfg->tbls); + if (qmp->submode =3D=3D UFS_HS_G4) + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4); qmp_ufs_pcs_init(qmp, &cfg->tbls); + if (qmp->submode =3D=3D UFS_HS_G4) + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4); } =20 static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -1021,6 +1029,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy= _mode mode, int submode) struct qmp_ufs *qmp =3D phy_get_drvdata(phy); =20 qmp->mode =3D mode; + qmp->submode =3D submode; =20 return 0; } --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CC2BC47089 for ; Thu, 1 Dec 2022 17:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230334AbiLARpC (ORCPT ); Thu, 1 Dec 2022 12:45:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230320AbiLARoa (ORCPT ); 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Thu, 01 Dec 2022 09:44:22 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 06/23] phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b Date: Thu, 1 Dec 2022 23:13:11 +0530 Message-Id: <20221201174328.870152-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 37 +++++++++++++++++++++---- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 82be9b754e8e..97d0baa9bac3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -214,8 +214,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -291,8 +292,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -357,8 +359,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -406,7 +409,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[]= =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), - }; =20 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { @@ -444,8 +446,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -679,6 +682,10 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -699,6 +706,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .pcs =3D sdm845_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sdm845_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -721,6 +732,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .pcs =3D sm6115_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm6115_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -743,6 +758,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .pcs =3D sm8150_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -763,6 +782,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -783,6 +806,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFBDDC43217 for ; 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Thu, 01 Dec 2022 09:44:29 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 07/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC Date: Thu, 1 Dec 2022 23:13:12 +0530 Message-Id: <20221201174328.870152-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 97d0baa9bac3..269f96a0f752 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -374,6 +374,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -411,6 +415,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), @@ -421,6 +444,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -762,6 +790,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .serdes =3D sm8150_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8150_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx =3D sm8150_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72506C43217 for ; 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Thu, 01 Dec 2022 09:44:35 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 08/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Date: Thu, 1 Dec 2022 23:13:13 +0530 Message-Id: <20221201174328.870152-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 62 ++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-ufs-v5.h index bcca23493b7e..3aa4232f84a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -13,6 +13,7 @@ #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 269f96a0f752..d5324c4e8513 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -449,6 +449,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_= g4_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), }; =20 +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -805,6 +833,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .regs =3D sm8150_ufsphy_regs_layout, }; =20 +static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D { + .lanes =3D 2, + + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 =3D { + .tx =3D sm8250_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx =3D sm8250_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list =3D sdm845_ufs_phy_clk_l, + .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8150_ufsphy_regs_layout, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 @@ -1297,7 +1357,7 @@ static const struct of_device_id qmp_ufs_of_match_tab= le[] =3D { .data =3D &sm8150_ufsphy_cfg, }, { .compatible =3D "qcom,sm8250-qmp-ufs-phy", - .data =3D &sm8150_ufsphy_cfg, + .data =3D &sm8250_ufsphy_cfg, }, { .compatible =3D "qcom,sm8350-qmp-ufs-phy", .data =3D &sm8350_ufsphy_cfg, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 297BBC43217 for ; Thu, 1 Dec 2022 17:45:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230367AbiLARpi (ORCPT ); Thu, 1 Dec 2022 12:45:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230309AbiLARpA (ORCPT ); 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Thu, 01 Dec 2022 09:44:43 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 09/23] phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers Date: Thu, 1 Dec 2022 23:13:14 +0530 Message-Id: <20221201174328.870152-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SM8350 default init sequence sets some PCS registers to HS G3, thereby disabling HS G4 mode. This has the effect on MPHY capability negotiation between the host and the device during link startup and causes the PA_MAXHSGEAR to G3 irrespective of device max gear. Due to that, the agreed gear speed determined by the UFS core will become G3 only and the platform won't run at G4. So, let's remove setting these registers for SM8350 as like other G4 compatible platforms. One downside of this is that, when the board design uses non-G4 compatible device, then MPHY will continue to run in the default mode (G4) even if UFSHCD runs in G3. But this is the case for other platforms as well. Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index d5324c4e8513..6c7c6a06fe3b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -567,13 +567,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; 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Thu, 01 Dec 2022 09:44:50 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:44:49 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 10/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC Date: Thu, 1 Dec 2022 23:13:15 +0530 Message-Id: <20221201174328.870152-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 6c7c6a06fe3b..75e55c4181c9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -571,6 +571,34 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -875,6 +903,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 392E7C4708E for ; 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Thu, 01 Dec 2022 09:44:56 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 11/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC Date: Thu, 1 Dec 2022 23:13:16 +0530 Message-Id: <20221201174328.870152-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 75e55c4181c9..96e03d4249da 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41C1EC47088 for ; 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Thu, 01 Dec 2022 09:45:03 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 12/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC Date: Thu, 1 Dec 2022 23:13:17 +0530 Message-Id: <20221201174328.870152-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 96e03d4249da..9f5526758985 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -763,6 +763,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83DBFC43217 for ; Thu, 1 Dec 2022 17:46:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230250AbiLARqY (ORCPT ); Thu, 1 Dec 2022 12:46:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230000AbiLARpt (ORCPT ); Thu, 1 Dec 2022 12:45:49 -0500 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 746D3B5DB7 for ; Thu, 1 Dec 2022 09:45:12 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id 130so2544150pfu.8 for ; Thu, 01 Dec 2022 09:45:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SEImNrrGJCLJR7lpSd2nSHN0zzQY9fzqQ71zihD+hPY=; b=abZ6cXJ5jEpFaBYzpmh43H4tsPfVt6pNfSbjqaUkYxoXHc1YeDebG+qIPFwFgY3yve DsLufoZGZPA7V30rvIHTUj6SAMbMslgXQ/VjI+uagzyAitDNv4Bszr0K0LWuyixnZ4rM g2gkHrG2uPN7xswI5gPSHuJd+jPZdgURBLhOYX3n2l0B9DtymQOh4tiQqtZN3rCOF32A wkULCIq6zD5DDJvrWxgtFMM995h9Ztozt9mSZgdLcoZxwWXkyQmxbq1+Q3b1Qiqx9PT7 1pt/uEnSDruS2W74zjEz6YL8FdaQuUnVFvo7m5ace8kp6IhBOgDWiCcqKUums/+6Mm5p kvMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SEImNrrGJCLJR7lpSd2nSHN0zzQY9fzqQ71zihD+hPY=; b=qo9blcJmAP155RMgHyzFisGomMrCHum9Vo8O/VMCu0icp+zel55Mcrp1MpUUI9cNtO vLwLkTI+h2MriyNQkk67H47fZxRM4RYZ0cerNzqokyT13adCXEl5TC1itOP+0Xwjkmuo GQ5gQncr6G2jIbdR/ecBqFJsWaiSbduylSQ5OfQpfial/vUf9L614lvy9okh52zmC30F 5DxCNxEQaVwy1nQk94of5/9twYdvYacef72gpOD0iUyQyK0x5ZgwHhx141i+Ko/6B6ZG bbZf2whWl4RHSzukC5jQjeJKPBjNMZ+IYh0FGguyWlNJ23Yhzt5r+LW0ngDaXoNEkFg2 ERgQ== X-Gm-Message-State: ANoB5pljF8MMi4hSQGR3lYFzDr4zmeLsuZl3Ij68zkwSujkuqmP56H6a 1pI68gHihnpkJtGKP5TA5QOc X-Google-Smtp-Source: AA0mqf6xxi+NiLugwTKa1a8nr6otS+6o/AZq2exeejeajSRynu2OEJXoy7j80va1kDe+Mp3k7eu4FA== X-Received: by 2002:a63:234e:0:b0:470:4222:c3ee with SMTP id u14-20020a63234e000000b004704222c3eemr60697272pgm.571.1669916711871; Thu, 01 Dec 2022 09:45:11 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:45:11 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 13/23] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Date: Thu, 1 Dec 2022 23:13:18 +0530 Message-Id: <20221201174328.870152-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" goto in error path is useful if the function needs to do cleanup other than returning the error code. But in this driver, goto statements are used for just returning the error code in many places. This really makes it hard to read the code. So let's get rid of those goto statements and just return the error code directly. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++--------------------- 1 file changed, 41 insertions(+), 59 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8ad1415e10b6..7cd996ac180b 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_= host *host) =20 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) { - int err =3D 0; + int err; struct device *dev =3D host->hba->dev; =20 if (host->is_lane_clks_enabled) @@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", host->rx_l0_sync_clk); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", host->tx_l0_sync_clk); @@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) goto disable_rx_l1; =20 host->is_lane_clks_enabled =3D true; - goto out; + + return 0; =20 disable_rx_l1: clk_disable_unprepare(host->rx_l1_sync_clk); @@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) clk_disable_unprepare(host->tx_l0_sync_clk); disable_rx_l0: clk_disable_unprepare(host->rx_l0_sync_clk); -out: + return err; } =20 @@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", &host->rx_l0_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", &host->tx_l0_sync_clk, false); if (err) - goto out; + return err; =20 /* In case of single lane per direction, don't read lane1 clocks */ if (host->hba->lanes_per_direction > 1) { err =3D ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", &host->rx_l1_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", &host->tx_l1_sync_clk, true); } -out: - return err; + + return 0; } =20 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) @@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) =20 if (!host->core_reset) { dev_warn(hba->dev, "%s: reset control not set\n", __func__); - goto out; + return 0; } =20 reenable_intr =3D hba->is_irq_enabled; @@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) if (ret) { dev_err(hba->dev, "%s: core_reset assert failed, err =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* @@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) hba->is_irq_enabled =3D true; } =20 -out: - return ret; + return 0; } =20 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; - int ret =3D 0; + int ret; bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; =20 /* Reset UFS Host Controller and PHY */ @@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) if (ret) { dev_err(hba->dev, "%s: phy init failed, ret =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* power on phy - start serdes and phy's power and clocks */ @@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) =20 out_disable_phy: phy_exit(phy); -out: + return ret; } =20 @@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *h= ba, static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate, bool update_link_startup_timer) { - int ret =3D 0; struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct ufs_clk_info *clki; u32 core_clk_period_in_ns; @@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, * Aggregation logic. */ if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) - goto out; + return 0; =20 if (gear =3D=3D 0) { dev_err(hba->dev, "%s: invalid gear =3D %d\n", __func__, gear); - goto out_error; + return -EINVAL; } =20 list_for_each_entry(clki, &hba->clk_list_head, list) { @@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, } =20 if (ufs_qcom_cap_qunipro(host)) - goto out; + return 0; =20 core_clk_period_in_ns =3D NSEC_PER_SEC / core_clk_rate; core_clk_period_in_ns <<=3D OFFSET_CLK_NS_REG; @@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rA)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rA[gear-1][1]; } else if (rate =3D=3D PA_HS_MODE_B) { @@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rB)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rB[gear-1][1]; } else { dev_err(hba->dev, "%s: invalid rate =3D %d\n", __func__, rate); - goto out_error; + return -EINVAL; } break; case SLOWAUTO_MODE: @@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(pwm_fr_table)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D pwm_fr_table[gear-1][1]; break; case UNCHANGED: default: dev_err(hba->dev, "%s: invalid mode =3D %d\n", __func__, hs); - goto out_error; + return -EINVAL; } =20 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=3D @@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u3= 2 gear, */ mb(); } - goto out; =20 -out_error: - ret =3D -EINVAL; -out: - return ret; + return 0; } =20 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, @@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, 0, true)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); - err =3D -EINVAL; - goto out; + return -EINVAL; } =20 if (ufs_qcom_cap_qunipro(host)) @@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, break; } =20 -out: return err; } =20 @@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, =20 if (!dev_req_params) { pr_err("%s: incoming dev_req_params is NULL\n", __func__); - ret =3D -EINVAL; - goto out; + return -EINVAL; } =20 switch (status) { @@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, if (ret) { pr_err("%s: failed to determine capabilities\n", __func__); - goto out; + return ret; } =20 /* enable the device ref clock before changing to HS mode */ @@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, ret =3D -EINVAL; break; } -out: + return ret; } =20 @@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(stru= ct ufs_hba *hba) err =3D ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), &pa_vs_config_reg1); if (err) - goto out; + return err; =20 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ - err =3D ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), (pa_vs_config_reg1 | (1 << 12))); - -out: - return err; } =20 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) @@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) =20 host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); if (!host) { - err =3D -ENOMEM; dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); - goto out; + return -ENOMEM; } =20 /* Make a two way bind between the qcom host and the hba */ @@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->rcdev.owner =3D dev->driver->owner; host->rcdev.nr_resets =3D 1; err =3D devm_reset_controller_register(dev, &host->rcdev); - if (err) { + if (err) dev_warn(dev, "Failed to register reset controller\n"); - err =3D 0; - } =20 if (!has_acpi_companion(dev)) { host->generic_phy =3D devm_phy_get(dev, "ufsphy"); @@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->dbg_print_en |=3D UFS_QCOM_DEFAULT_DBG_PRINT_EN; ufs_qcom_get_default_testbus_cfg(host); err =3D ufs_qcom_testbus_config(host); - if (err) { + if (err) + /* Failure is non-fatal */ dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); - err =3D 0; - } =20 - goto out; + return 0; =20 out_variant_clear: ufshcd_set_variant(hba, NULL); -out: + return err; } =20 @@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_di= v(struct ufs_hba *hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); if (err) - goto out; + return err; =20 core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; core_clk_ctrl_reg |=3D clk_cycles; @@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_d= iv(struct ufs_hba *hba, /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; =20 - err =3D ufshcd_dme_set(hba, + return ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); -out: - return err; } =20 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) @@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, =20 if (err || !dev_req_params) { ufshcd_uic_hibern8_exit(hba); - goto out; + return err; } =20 ufs_qcom_cfg_timers(hba, @@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, ufshcd_uic_hibern8_exit(hba); } =20 -out: - return err; + return 0; } =20 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49066C43217 for ; Thu, 1 Dec 2022 17:46:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbiLARqr (ORCPT ); Thu, 1 Dec 2022 12:46:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230419AbiLARqE (ORCPT ); Thu, 1 Dec 2022 12:46:04 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41130CAB72 for ; Thu, 1 Dec 2022 09:45:19 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id k5so2509207pjo.5 for ; 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Thu, 01 Dec 2022 09:45:18 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:45:17 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 14/23] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Date: Thu, 1 Dec 2022 23:13:19 +0530 Message-Id: <20221201174328.870152-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the reset assert and deassert callbacks, the supplied "id" is not used at all and only the hba reset is performed all the time. So there is no reason to use a WARN_ON on the "id". Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 7cd996ac180b..8bb0f4415f1a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -895,8 +895,6 @@ ufs_qcom_reset_assert(struct reset_controller_dev *rcde= v, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_assert_reset(host->hba); /* provide 1ms delay to let the reset pulse propagate. */ usleep_range(1000, 1100); @@ -908,8 +906,6 @@ ufs_qcom_reset_deassert(struct reset_controller_dev *rc= dev, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_deassert_reset(host->hba); =20 /* --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 478DCC4321E for ; Thu, 1 Dec 2022 17:47:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230335AbiLARrC (ORCPT ); Thu, 1 Dec 2022 12:47:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230126AbiLARqU (ORCPT ); Thu, 1 Dec 2022 12:46:20 -0500 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8011B8440 for ; Thu, 1 Dec 2022 09:45:25 -0800 (PST) Received: by mail-pf1-x42e.google.com with SMTP id w2so1021305pfq.12 for ; Thu, 01 Dec 2022 09:45:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=eKGYk7xyAQavSQBsjlzuDbYsvnfff8yRZnJrY1iOT7xZ147x2NChnagbYy5Bug4TEt wRJ6IWNneM9GBMiBn5Qo5XMr7ai+GLKhAnsMFjFOeYIosJheOB1X0A3+0Lr1ykOSlaow YAj3IxkYDt4xedk0ozbTm7WSErdtWYLYYuVly5BoXgI0zCgv7SmHMISwsKBTFf+IPoDR H0DH8q2yMj7s9DTyMrjp+Six+OUz2vXG4JYZ1JaODIGSBlemIVTDdLIZlarRfoGBDnSE 0DI7Fdpwmvh8xAWumCdbAX2Vn0m2X3py2bjxZwrrEjvTMDLWjTMIn6LK7qhPUj+GSTZm L9pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=ir7x7l1lShcjeLzIo4cV7uOmEssGOJPR/EOmrC5jM37tT0MxWI1niMdPrOA3Lpwpkt 5YECGjUY4cO4e/JoCtotm6DlAJGneourpUSAZ5MEyTDDTdF0KidW/jZSDAJs/YUSYwvh 45IqAuifVAeYCcO5uFRyc+Ye/xtcj0SPuYN6Ff1I5Zg3egDxB0zskY2rD4ksSu9SMEJ7 KlwnVscEbaRnZ3y+4WqMuleYzzVj8jsHN1yYWUpsDT5Vn2O2lQx8qeXwHNsddtpZzpFV JTDr32zkd6bqgzMuA2hfLI73cdSQXhKqESqz6wMOnLO6DaGNC8fMeYDf5il6Ssg1pPXX R3uQ== X-Gm-Message-State: ANoB5pmM3x4LDyEdYVVoOxRT0QNc//0dORtisAbVktZhFi2z6HSYhXOf cYyK45QlV/oqUPuxQuhlFz54 X-Google-Smtp-Source: AA0mqf4aw+b6Q2ybWbv0ykzh0c6ES1kHCCxJE3v3NuIOFrOG40c+1VVzFTtl2Fkhj+/T69gHXFjWmA== X-Received: by 2002:a65:5781:0:b0:470:1b:f65c with SMTP id b1-20020a655781000000b00470001bf65cmr52099444pgr.199.1669916725285; Thu, 01 Dec 2022 09:45:25 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:45:24 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 15/23] scsi: ufs: ufs-qcom: Use bitfields where appropriate Date: Thu, 1 Dec 2022 23:13:20 +0530 Message-Id: <20221201174328.870152-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use bitfield macros where appropriate to simplify the driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 44466a395bb5..9d96ac71b27f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -17,12 +17,9 @@ #define DEFAULT_CLK_RATE_HZ 1000000 #define BUS_VECTOR_NAME_LEN 32 =20 -#define UFS_HW_VER_MAJOR_SHFT (28) -#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) -#define UFS_HW_VER_MINOR_SHFT (16) -#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) -#define UFS_HW_VER_STEP_SHFT (0) -#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) +#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) +#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) +#define UFS_HW_VER_STEP_MASK GENMASK(15, 0) =20 /* vendor specific pre-defined parameters */ #define SLOW 1 @@ -76,24 +73,28 @@ enum { #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) =20 /* bit definitions for REG_UFS_CFG1 register */ -#define QUNIPRO_SEL 0x1 -#define UTP_DBG_RAMS_EN 0x20000 +#define QUNIPRO_SEL BIT(0) +#define UFS_PHY_SOFT_RESET BIT(1) +#define UTP_DBG_RAMS_EN BIT(17) #define TEST_BUS_EN BIT(18) #define TEST_BUS_SEL GENMASK(22, 19) #define UFS_REG_TEST_BUS_EN BIT(30) =20 +#define UFS_PHY_RESET_ENABLE 1 +#define UFS_PHY_RESET_DISABLE 0 + /* bit definitions for REG_UFS_CFG2 register */ -#define UAWM_HW_CGC_EN (1 << 0) -#define UARM_HW_CGC_EN (1 << 1) -#define TXUC_HW_CGC_EN (1 << 2) -#define RXUC_HW_CGC_EN (1 << 3) -#define DFC_HW_CGC_EN (1 << 4) -#define TRLUT_HW_CGC_EN (1 << 5) -#define TMRLUT_HW_CGC_EN (1 << 6) -#define OCSC_HW_CGC_EN (1 << 7) +#define UAWM_HW_CGC_EN BIT(0) +#define UARM_HW_CGC_EN BIT(1) +#define TXUC_HW_CGC_EN BIT(2) +#define RXUC_HW_CGC_EN BIT(3) +#define DFC_HW_CGC_EN BIT(4) +#define TRLUT_HW_CGC_EN BIT(5) +#define TMRLUT_HW_CGC_EN BIT(6) +#define OCSC_HW_CGC_EN BIT(7) =20 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ -#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide = */ +#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ @@ -101,17 +102,11 @@ enum { TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) =20 /* bit offset */ -enum { - OFFSET_UFS_PHY_SOFT_RESET =3D 1, - OFFSET_CLK_NS_REG =3D 10, -}; +#define OFFSET_CLK_NS_REG 0xa =20 /* bit masks */ -enum { - MASK_UFS_PHY_SOFT_RESET =3D 0x2, - MASK_TX_SYMBOL_CLK_1US_REG =3D 0x3FF, - MASK_CLK_NS_REG =3D 0xFFFC00, -}; +#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) +#define MASK_CLK_NS_REG GENMASK(23, 10) =20 /* QCOM UFS debug print bit mask */ #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) @@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, { u32 ver =3D ufshcd_readl(hba, REG_UFS_HW_VERSION); =20 - *major =3D (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT; - *minor =3D (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT; - *step =3D (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT; + *major =3D FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); + *minor =3D FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); + *step =3D FIELD_GET(UFS_HW_VER_STEP_MASK, ver); }; =20 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_ENABLE), + REG_UFS_CFG1); =20 /* * Make sure assertion of ufs phy reset is written to @@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba= *hba) =20 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_DISABLE), + REG_UFS_CFG1); =20 /* * Make sure de-assertion of ufs phy reset is written to --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51D62C43217 for ; Thu, 1 Dec 2022 17:47:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229807AbiLARrN (ORCPT ); Thu, 1 Dec 2022 12:47:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230267AbiLARql (ORCPT ); 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Thu, 01 Dec 2022 09:45:30 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 16/23] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Date: Thu, 1 Dec 2022 23:13:21 +0530 Message-Id: <20221201174328.870152-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make use of dev_err_probe() for printing the probe error. Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8bb0f4415f1a..38e2ed749d75 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1441,9 +1441,9 @@ static int ufs_qcom_probe(struct platform_device *pde= v) /* Perform generic probe */ err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); if (err) - dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); + return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); =20 - return err; + return 0; } =20 /** --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47B33C43217 for ; Thu, 1 Dec 2022 17:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230472AbiLARr0 (ORCPT ); Thu, 1 Dec 2022 12:47:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229973AbiLARqv (ORCPT ); Thu, 1 Dec 2022 12:46:51 -0500 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CF5CB71EE for ; Thu, 1 Dec 2022 09:45:38 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id 130so2545360pfu.8 for ; Thu, 01 Dec 2022 09:45:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dxBfeAGPJSh5Y/5FKQg+M0y4cyLZHfyLwZKtosIJVD4=; b=cVwgxrvy/wOo/YjbpaKogtDcuRpXMD+mUA4GkYeUOI6ezInGYpeliOJhgIJry0ziLR 8y9LGTbBtBmeMdV/H8LCPq3vDwErrNqkT9rgREnBoj3DsUMM1DopJr76+l6mMKCBpxJu zmMZN4Bah9vgAJWZDusTqfvblRNVK4s8q3kahKW9bwfUHWxxlZm0ixfbpawBuguxhREf UfvY4NEIePA5J+Qi8PGi5o6eTWE3eJ3zuKPx6VPJaNQ76kUG2CBWQ5Qe/oD+9AtYmR/s FEgVg6l1SkCWtxOLanu3bXfrK0hyRTrvYJqivFlLYP92MKJNPayoF7ims3T9syyvtCTT NqDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dxBfeAGPJSh5Y/5FKQg+M0y4cyLZHfyLwZKtosIJVD4=; b=jHrXykSuPXtzsPfbHGe+2Rdod1XkUeE8r5VtVkpjCneeVHQY+jmAEv7e9P8Z9ETeGg FBOTTX/p7xwGmubm9olkwhgAc9/ZUlc+Errqc4HCajno/dsXo0XKzCgGc+QKHgecBtpd GbT8V1JhIUmM/W1hOg/o7P039PZ813qMiT0FM7DXL2i53EPhKM5VnfRrGCjX6eXBPse7 UAD3W3pTv3QseMXm7hr4n4N2t0Mr4aeCyydn276QvxRdsmDuJUtXwxhwz2vkNusL6Aj3 pr5Ee6cQhg+NzcG9AnNp9ZmnTPiEVn+NBIfHabnScxCgp1hp93EY67mfLV5M7ZEVl3Qh LXLA== X-Gm-Message-State: ANoB5pktOw576RRlj40ROQIsGrKAHS14Cl6w9BwlnEZuzUWsn4P4E8G5 HdrbQYBLLObIbbpuCgax7MsP X-Google-Smtp-Source: AA0mqf5Mgc99o/UTJhLXzyZGQaJIysEcv5YHIa6ydHMeEjKzcZ4+/ZNExCZfxzP0xAEDdC+jXRyw0w== X-Received: by 2002:a05:6a00:f8a:b0:56c:2576:9d2a with SMTP id ct10-20020a056a000f8a00b0056c25769d2amr49815642pfb.60.1669916737965; Thu, 01 Dec 2022 09:45:37 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:45:37 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 17/23] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Date: Thu, 1 Dec 2022 23:13:22 +0530 Message-Id: <20221201174328.870152-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On newer UFS revisions, the register at offset 0xD0 is called, REG_UFS_PARAM0. Since the existing register, RETRY_TIMER_REG is not used anywhere, it is safe to use the new name. Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9d96ac71b27f..7fe928b82753 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -33,7 +33,8 @@ enum { REG_UFS_TX_SYMBOL_CLK_NS_US =3D 0xC4, REG_UFS_LOCAL_PORT_ID_REG =3D 0xC8, REG_UFS_PA_ERR_CODE =3D 0xCC, - REG_UFS_RETRY_TIMER_REG =3D 0xD0, + /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ + REG_UFS_PARAM0 =3D 0xD0, REG_UFS_PA_LINK_STARTUP_TIMER =3D 0xD8, REG_UFS_CFG1 =3D 0xDC, REG_UFS_CFG2 =3D 0xE0, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78C21C43217 for ; Thu, 1 Dec 2022 17:47:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230525AbiLARrj (ORCPT ); Thu, 1 Dec 2022 12:47:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230022AbiLARq7 (ORCPT ); Thu, 1 Dec 2022 12:46:59 -0500 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8509BB000 for ; Thu, 1 Dec 2022 09:45:45 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id 130so2545744pfu.8 for ; Thu, 01 Dec 2022 09:45:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L8CMRsJAWw5Kl2y6C4bQ/udAroFdc5lkzkoFkDtAV0k=; b=L9ZGHIuIN4pPpIQ02mKvPDbt7rsp+sys+Lik1R2XQTVkFu+uRC89PbR+dZwc52D8Q7 g11NpkjDgJTJiTpWG/PbIwmXqJ22q/CAgB0sdJB4kjkpmvKdGsfzPUJFka0G9hBGXSka qfMUADxnUudncW+CM4fhFdPDrOiQuhVjxu4Fx8YZPXJuni6pnL07h9Y4l9+cyKgoJz23 CEUnpzZoPOyMDeBy9l5ALrJI/57dx03ck+PieN6055E5ZoB9AR7kZ5Gum8iHrUAah0RB Qxn2i9gkfZe4YxEgUpH2qSa9m/9fqpxXD5UuKg0mY4EY8J+PGfD0JHGQu12n0WhzJJyL z7pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L8CMRsJAWw5Kl2y6C4bQ/udAroFdc5lkzkoFkDtAV0k=; b=0TaExBsOs+kHKNsY41UV2JrFyXsM3YBiLDQZTXo6qIALlkYF45mzpWiUUnFjMmV2z1 RwxdDRI/BwGsZPtRegknYGbRSOKWhiFIJUqgFwvShiJ+eJv68ajfhYW6ECN4eN7u47bF POSIKVGoY0halkrNh29P0b5iLeRLuAp2KywwDtPnUZpQqt6NVlSbedG9tYzQgP0HITlV UmvALgZRinSjewTFUZ2ByG5mYA0J7IBeZV7GM1uZEJHQqmMS8wpDjrOBtF7ITYdIZCIj HDSRmaGXflsq5F8eNmKUmp+qThWdmJz0duP5+QFQNIEel4Q6zoBSAPFeyaSltmwKnHgs hZMg== X-Gm-Message-State: ANoB5plP3jwiGjgCBUn/9GwvOaKbM9bAlYSYGFDDI6UR3GuMSJQvuisy zqJ9WdXxDF5wFU8HWLwWJim+ X-Google-Smtp-Source: AA0mqf7y7AzxCwbyVg7CsylxaJhKbOLur7jj9QPpD1O9t/GU02NyTqdu+AdHJk3FLBpzUInJiq6H1w== X-Received: by 2002:a63:2361:0:b0:477:b603:f683 with SMTP id u33-20020a632361000000b00477b603f683mr39094258pgm.93.1669916745385; Thu, 01 Dec 2022 09:45:45 -0800 (PST) Received: from localhost.localdomain ([220.158.159.39]) by smtp.gmail.com with ESMTPSA id p4-20020a170902780400b0016d9b101413sm3898743pll.200.2022.12.01.09.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 09:45:44 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 18/23] scsi: ufs: core: Add reinit_notify() callback Date: Thu, 1 Dec 2022 23:13:23 +0530 Message-Id: <20221201174328.870152-19-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" reinit_notify() callback can be used by the UFS controllers to perform changes required for UFS core reinit. Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/core/ufshcd-priv.h | 6 ++++++ include/ufs/ufshcd.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index a9e8e1f5afe7..2ce3c98e0711 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -226,6 +226,12 @@ static inline void ufshcd_vops_config_scaling_param(st= ruct ufs_hba *hba, hba->vops->config_scaling_param(hba, p, data); } =20 +static inline void ufshcd_vops_reinit_notify(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->reinit_notify) + hba->vops->reinit_notify(hba); +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; =20 /** diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 5cf81dff60aa..af8c95077d96 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -297,6 +297,7 @@ struct ufs_pwr_mode_info { * @config_scaling_param: called to configure clock scaling parameters * @program_key: program or evict an inline encryption key * @event_notify: called to notify important events + * @reinit_notify: called to notify UFS core reinit */ struct ufs_hba_variant_ops { const char *name; @@ -335,6 +336,7 @@ struct ufs_hba_variant_ops { const union ufs_crypto_cfg_entry *cfg, int slot); void (*event_notify)(struct ufs_hba *hba, enum ufs_event_type evt, void *data); + void (*reinit_notify)(struct ufs_hba *); }; =20 /* clock gating state */ --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CC3EC43217 for ; Thu, 1 Dec 2022 17:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231144AbiLARsB (ORCPT ); Thu, 1 Dec 2022 12:48:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230354AbiLARrL (ORCPT ); Thu, 1 Dec 2022 12:47:11 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9537EBB022 for ; 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charset="utf-8" Some platforms like Qcom, requires the UFS device to be reinitialized after switching to maximum gear speed. So add support for that in UFS core by introducing a new quirk (UFSHCD_CAP_REINIT_AFTER_MAX_GEAR_SWITCH) and doing the reinitialization, if the quirk is enabled by the controller driver. Suggested-by: Can Guo Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/core/ufshcd.c | 63 +++++++++++++++++++++++++++++---------- include/ufs/ufshcd.h | 6 ++++ 2 files changed, 53 insertions(+), 16 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index e18c9f4463ec..55714accdfd4 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8153,27 +8153,18 @@ static int ufshcd_add_lus(struct ufs_hba *hba) return ret; } =20 -/** - * ufshcd_probe_hba - probe hba to detect device and initialize it - * @hba: per-adapter instance - * @init_dev_params: whether or not to call ufshcd_device_params_init(). - * - * Execute link-startup and verify device initialization - */ -static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) { int ret; - unsigned long flags; - ktime_t start =3D ktime_get(); =20 hba->ufshcd_state =3D UFSHCD_STATE_RESET; =20 ret =3D ufshcd_link_startup(hba); if (ret) - goto out; + return ret; =20 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) - goto out; + return ret; =20 /* Debug counters initialization */ ufshcd_clear_dbg_ufs_stats(hba); @@ -8184,12 +8175,12 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bo= ol init_dev_params) /* Verify device initialization by sending NOP OUT UPIU */ ret =3D ufshcd_verify_dev_init(hba); if (ret) - goto out; + return ret; =20 /* Initiate UFS initialization, and waiting until completion */ ret =3D ufshcd_complete_dev_init(hba); if (ret) - goto out; + return ret; =20 /* * Initialize UFS device parameters used by driver, these @@ -8198,7 +8189,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool= init_dev_params) if (init_dev_params) { ret =3D ufshcd_device_params_init(hba); if (ret) - goto out; + return ret; } =20 ufshcd_tune_unipro_params(hba); @@ -8219,11 +8210,51 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bo= ol init_dev_params) if (ret) { dev_err(hba->dev, "%s: Failed setting power mode, err =3D %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +/** + * ufshcd_probe_hba - probe hba to detect device and initialize it + * @hba: per-adapter instance + * @init_dev_params: whether or not to call ufshcd_device_params_init(). + * + * Execute link-startup and verify device initialization + */ +static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +{ + ktime_t start =3D ktime_get(); + unsigned long flags; + int ret; + + ret =3D ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; + + if (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) { + /* Reset the device and controller before doing reinit */ + ufshcd_device_reset(hba); + ufshcd_hba_stop(hba); + ufshcd_vops_reinit_notify(hba); + ret =3D ufshcd_hba_enable(hba); + if (ret) { + dev_err(hba->dev, "Host controller enable failed\n"); + ufshcd_print_evt_hist(hba); + ufshcd_print_host_state(hba); goto out; } - ufshcd_print_pwr_info(hba); + + /* Reinit the device */ + ret =3D ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; } =20 + ufshcd_print_pwr_info(hba); + /* * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) * and for removable UFS card as well, hence always set the parameter. diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index af8c95077d96..443403d3be72 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -595,6 +595,12 @@ enum ufshcd_quirks { * auto-hibernate capability but it's FASTAUTO only. */ UFSHCD_QUIRK_HIBERN_FASTAUTO =3D 1 << 18, + + /* + * This quirk needs to be enabled if the host controller needs + * to reinit the device after switching to maximum gear. + */ + UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH =3D 1 << 19, }; =20 enum ufshcd_caps { --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BD26C43217 for ; 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Thu, 01 Dec 2022 09:45:56 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 20/23] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Date: Thu, 1 Dec 2022 23:13:25 +0530 Message-Id: <20221201174328.870152-21-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the preparation of adding support for new gears, let's move the logic that finds the gear for each platform to a new function. This helps with code readability and also allows the logic to be used in other places of the driver in future. While at it, let's make it clear that this driver only supports symmetric gear setting (hs_tx_gear =3D=3D hs_rx_gear). Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 38e2ed749d75..919b6eae439d 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -278,6 +278,25 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) return 0; } =20 +static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + + if (host->hw_ver.major =3D=3D 0x1) { + /* + * HS-G3 operations may not reliably work on legacy QCOM + * UFS host controller hardware even though capability + * exchange during link startup phase may end up + * negotiating maximum supported gear as G3. + * Hence downgrade the maximum supported gear to HS-G2. + */ + return UFS_HS_G2; + } + + /* Default is HS-G3 */ + return UFS_HS_G3; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -692,19 +711,8 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *= hba, ufshcd_init_pwr_dev_param(&ufs_qcom_cap); ufs_qcom_cap.hs_rate =3D UFS_QCOM_LIMIT_HS_RATE; =20 - if (host->hw_ver.major =3D=3D 0x1) { - /* - * HS-G3 operations may not reliably work on legacy QCOM - * UFS host controller hardware even though capability - * exchange during link startup phase may end up - * negotiating maximum supported gear as G3. - * Hence downgrade the maximum supported gear to HS-G2. - */ - if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_tx_gear =3D UFS_HS_G2; - if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_rx_gear =3D UFS_HS_G2; - } + /* This driver only supports symmetic gear setting i.e., hs_tx_gear =3D= =3D hs_rx_gear */ + ufs_qcom_cap.hs_tx_gear =3D ufs_qcom_cap.hs_rx_gear =3D ufs_qcom_get_hs_= gear(hba); =20 ret =3D ufshcd_get_pwr_dev_param(&ufs_qcom_cap, dev_max_params, --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12B33C43217 for ; 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Thu, 01 Dec 2022 09:46:03 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 21/23] scsi: ufs: ufs-qcom: Add support for reinitializing the UFS device Date: Thu, 1 Dec 2022 23:13:26 +0530 Message-Id: <20221201174328.870152-22-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting from Qualcomm UFS version 4, the UFS device needs to be reinitialized after switching to maximum gear by the UFS core. Hence, add support for it by enabling the UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH quirk, implementing reinit_notify() callback and using the agreed gear speed for setting the PHY mode. Suggested-by: Can Guo Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.c | 26 ++++++++++++++++++++++---- drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 919b6eae439d..3efef2f36e69 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -302,7 +302,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; int ret; - bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; =20 /* Reset UFS Host Controller and PHY */ ret =3D ufs_qcom_host_reset(hba); @@ -310,9 +309,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) dev_warn(hba->dev, "%s: host reset returned %d\n", __func__, ret); =20 - if (is_rate_B) - phy_set_mode(phy, PHY_MODE_UFS_HS_B); - /* phy initialization - calibrate the phy */ ret =3D phy_init(phy); if (ret) { @@ -321,6 +317,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) return ret; } =20 + phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); + /* power on phy - start serdes and phy's power and clocks */ ret =3D phy_power_on(phy); if (ret) { @@ -723,6 +721,9 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, return ret; } =20 + /* Use the agreed gear */ + host->hs_gear =3D dev_req_params->gear_tx; + /* enable the device ref clock before changing to HS mode */ if (!ufshcd_is_hs_mode(&hba->pwr_info) && ufshcd_is_hs_mode(dev_req_params)) @@ -836,6 +837,9 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *h= ba) | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); } + + if (host->hw_ver.major > 0x3) + hba->quirks |=3D UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; } =20 static void ufs_qcom_set_caps(struct ufs_hba *hba) @@ -1044,6 +1048,12 @@ static int ufs_qcom_init(struct ufs_hba *hba) dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); =20 + /* + * Power up the PHY using the minimum supported gear (UFS_HS_G2). + * Switching to max gear will be performed during reinit if supported. + */ + host->hs_gear =3D UFS_HS_G2; + return 0; =20 out_variant_clear: @@ -1410,6 +1420,13 @@ static void ufs_qcom_config_scaling_param(struct ufs= _hba *hba, } #endif =20 +static void ufs_qcom_reinit_notify(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + + phy_power_off(host->generic_phy); +} + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1433,6 +1450,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_= vops =3D { .device_reset =3D ufs_qcom_device_reset, .config_scaling_param =3D ufs_qcom_config_scaling_param, .program_key =3D ufs_qcom_ice_program_key, + .reinit_notify =3D ufs_qcom_reinit_notify, }; =20 /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 7fe928b82753..4b00c67e9d7f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -217,6 +217,8 @@ struct ufs_qcom_host { struct reset_controller_dev rcdev; =20 struct gpio_desc *device_reset; + + u32 hs_gear; }; =20 static inline u32 --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C2FEC43217 for ; Thu, 1 Dec 2022 17:49:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231206AbiLARtA (ORCPT ); Thu, 1 Dec 2022 12:49:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230354AbiLARsI (ORCPT ); Thu, 1 Dec 2022 12:48:08 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1E36BA095 for ; Thu, 1 Dec 2022 09:46:10 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id u15-20020a17090a3fcf00b002191825cf02so2816890pjm.2 for ; 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charset="utf-8" Starting from Qcom UFS version 4.0, vendor specific REG_UFS_PARAM0 register can be used to determine the maximum gear supported by the controller. Suggested-by: Can Guo Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- drivers/ufs/host/ufs-qcom.c | 2 ++ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 3efef2f36e69..607fddb7b4c3 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -291,6 +291,8 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) * Hence downgrade the maximum supported gear to HS-G2. */ return UFS_HS_G2; + } else if (host->hw_ver.major >=3D 0x4) { + return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); } =20 /* Default is HS-G3 */ diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 4b00c67e9d7f..dd3abd23ec22 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -94,6 +94,10 @@ enum { #define TMRLUT_HW_CGC_EN BIT(6) #define OCSC_HW_CGC_EN BIT(7) =20 +/* bit definitions for REG_UFS_PARAM0 */ +#define MAX_HS_GEAR_MASK GENMASK(6, 4) +#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) + /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 --=20 2.25.1 From nobody Thu Sep 18 21:41:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A817CC43217 for ; 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Thu, 01 Dec 2022 09:46:14 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v4 23/23] MAINTAINERS: Add myself as the maintainer for Qcom UFS drivers Date: Thu, 1 Dec 2022 23:13:28 +0530 Message-Id: <20221201174328.870152-24-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom UFS drivers are left un-maintained till now. I'd like to step up to maintain the drivers and the binding. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Andersson Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3583c5f6889d..3c8214f4a3cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21379,6 +21379,14 @@ L: linux-mediatek@lists.infradead.org (moderated f= or non-subscribers) S: Maintained F: drivers/ufs/host/ufs-mediatek* =20 +UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER QUALCOMM HOOKS +M: Manivannan Sadhasivam +L: linux-arm-msm@vger.kernel.org +L: linux-scsi@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +F: drivers/ufs/host/ufs-qcom* + UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER RENESAS HOOKS M: Yoshihiro Shimoda L: linux-renesas-soc@vger.kernel.org --=20 2.25.1