From nobody Thu Sep 18 23:34:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7007C43217 for ; Thu, 1 Dec 2022 12:40:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231448AbiLAMkP (ORCPT ); Thu, 1 Dec 2022 07:40:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231264AbiLAMkM (ORCPT ); Thu, 1 Dec 2022 07:40:12 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 012685AE32 for ; Thu, 1 Dec 2022 04:40:09 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id q71so1554525pgq.8 for ; Thu, 01 Dec 2022 04:40:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iMerckrhZTm3FZ8D21RolrP9vW5vY1yytNXMfvZLbSs=; b=EW5N4fofLG283DGbnT+a/zHyAd4+0YOIWw6FGWlEpchFEMUJzLqhZWhWABAWelWgmp tYxkMY+aOjTkvgYbcPfiocKATHcS4FrKB9hHvgGE0qojBUvWf549A1krIqY3kTKEkQUt qBCFDeFj/9xscbLvW3OKFoVDxvmOSMe2vsQSrPEb+sikXyxGMCzD+eyP8SiY8DP5H88C aghhCxchlMILuAzqq0/vxFOIK7KUzgwIYWlErfBS5HM012J0kQSo8C/6OCx2xlYJvQLh SkpVTk52AuEe/ntV8JBSkQ01QQRqe38fI5aNMZk7pb+mXZcYuQuzK61yGSDiGUncfFke H+sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iMerckrhZTm3FZ8D21RolrP9vW5vY1yytNXMfvZLbSs=; b=XxXSA2R29Kj7HifXX4GXEB9Uix30IF4M5kztPPxXFPeOYzw8B9V38jmIoLHpT+KCG3 1MVR2Q8LaaeOpbXOS4MPwP6jm/PVUIa5XdwxySj6UPNRvOfpTnTajpHaz++69/ZyHpql dyJdtIHCkDK910YsgPcD9w1dIeO2eSu0u1U0uRskx8fKvzWXVAMi6yJ2c0LsXrdhjFX5 DyqjrHc+jzEPvoccXi455lDKSzQ3lRsyxISORjefXW8zE/GRwgrKqLM0CY4534MfXMZ0 l3gLYqZBzTsxiqK+DD/kOiwytH16Rfs+bjWi3knITTISdB7Y+uQNnK+IA3oICTYK73xo 7mrQ== X-Gm-Message-State: ANoB5pl3VmpR6lglPFQmnPLP5TGazuUZ3Vo0iV3GC429talOLwEOuq26 D2I3OYYkIbQB59dRRx/sNJtrow== X-Google-Smtp-Source: AA0mqf782l4m814ZaZs0CFvnLfiiFisNyRXUDu+bIqwsD0IywGmhZJf0DMxA/y+agEoh/mh+ymv4Yg== X-Received: by 2002:a05:6a00:10cd:b0:572:5c03:f7ad with SMTP id d13-20020a056a0010cd00b005725c03f7admr67744766pfu.17.1669898409211; Thu, 01 Dec 2022 04:40:09 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.81.69]) by smtp.gmail.com with ESMTPSA id b65-20020a62cf44000000b0056f0753390csm3246981pfg.96.2022.12.01.04.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 04:40:08 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Conor Dooley , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt Subject: [PATCH v5 1/3] RISC-V: time: initialize hrtimer based broadcast clock event device Date: Thu, 1 Dec 2022 18:09:52 +0530 Message-Id: <20221201123954.1111603-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221201123954.1111603-1-apatel@ventanamicro.com> References: <20221201123954.1111603-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Similarly to commit 022eb8ae8b5e ("ARM: 8938/1: kernel: initialize broadcast hrtimer based clock event device"), RISC-V needs to initiate hrtimer based broadcast clock event device before C3STOP can be used. Otherwise, the introduction of C3STOP for the RISC-V arch timer in commit 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend") leaves us without any broadcast timer registered. This prevents the kernel from entering oneshot mode, which breaks timer behaviour, for example clock_nanosleep(). A test app that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=3D250 & C3STOP enabled, the sleep times are rounded up to the next jiffy: =3D=3D CPU: 1 =3D=3D =3D=3D CPU: 2 =3D=3D =3D=3D CPU: 3 =3D=3D = =3D=3D CPU: 4 =3D=3D Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179 Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193 Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000 Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000 Samples: 521 Samples: 521 Samples: 521 Samples: 521 Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/ Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during = CPU suspend") Suggested-by: Samuel Holland Signed-off-by: Conor Dooley Reviewed-by: Samuel Holland Acked-by: Palmer Dabbelt --- arch/riscv/kernel/time.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index 8217b0f67c6c..1cf21db4fcc7 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -29,6 +30,8 @@ void __init time_init(void) =20 of_clk_init(NULL); timer_probe(); + + tick_setup_hrtimer_broadcast(); } =20 void clocksource_arch_init(struct clocksource *cs) --=20 2.34.1 From nobody Thu Sep 18 23:34:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0D72C43217 for ; Thu, 1 Dec 2022 12:40:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231469AbiLAMkW (ORCPT ); Thu, 1 Dec 2022 07:40:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231460AbiLAMkQ (ORCPT ); Thu, 1 Dec 2022 07:40:16 -0500 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 917655E9E4 for ; Thu, 1 Dec 2022 04:40:15 -0800 (PST) Received: by mail-pg1-x52c.google.com with SMTP id 6so1560685pgm.6 for ; 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Thu, 01 Dec 2022 04:40:14 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.81.69]) by smtp.gmail.com with ESMTPSA id b65-20020a62cf44000000b0056f0753390csm3246981pfg.96.2022.12.01.04.40.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 04:40:14 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Conor Dooley , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v5 2/3] dt-bindings: timer: Add bindings for the RISC-V timer device Date: Thu, 1 Dec 2022 18:09:53 +0530 Message-Id: <20221201123954.1111603-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221201123954.1111603-1-apatel@ventanamicro.com> References: <20221201123954.1111603-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings for a separate RISC-V timer DT node which can be used to describe implementation specific behaviour (such as timer interrupt not triggered during non-retentive suspend). Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Reviewed-by: Rob Herring --- .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Doc= umentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 000000000000..38d67e1a5a79 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mo= de + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cannot-wake-cpu: + type: boolean + description: + If present, the timer interrupt cannot wake up the CPU from one or + more suspend/idle states. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible =3D "riscv,timer"; + interrupts-extended =3D <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +... --=20 2.34.1 From nobody Thu Sep 18 23:34:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7AF3C43217 for ; Thu, 1 Dec 2022 12:40:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231234AbiLAMkf (ORCPT ); Thu, 1 Dec 2022 07:40:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231477AbiLAMk3 (ORCPT ); Thu, 1 Dec 2022 07:40:29 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B37EBA0A6 for ; Thu, 1 Dec 2022 04:40:21 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id u15-20020a17090a3fcf00b002191825cf02so1916548pjm.2 for ; Thu, 01 Dec 2022 04:40:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6S7naxVeL+Tq1XdOeQt8X5QpTYGWrVZhiHOlENIaVW4=; b=ODFqGsjSBR77IhnwGSMqT5Cedqv+o+83HTdoL9r+54VqgGotTXmXpohITgE49F7wSd Tkur0/NYoqgk92i4gk54CRC/pqYBBmM2Zbo6r10FLJYhD2qqf8jup2GHELUwP4gwflmR zHYM7ShhCJW76jq1Qu2vQBginDdz04Pbwt71TzSOIEVOWuPV44OgVizwpklWWnB7e+Y5 D4+z2VkQ+x3EEWAciK1knsKdG5FhwxYEmrPWeSjvn7rHX4xtesNCG3kcL9kYwyxbC5ya FHhXlzp0mt54IMjKmv9qfrLyPhAifG9KdRWdez3fjVDG0RQP0zP5aj9Gdf9VUb814ry7 1cfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6S7naxVeL+Tq1XdOeQt8X5QpTYGWrVZhiHOlENIaVW4=; b=tOyoPHnHd2giSZmDqP4RsQMJ5TdEzaR9ko6b/BBHu/2hQvCX70k+842xmLNldYX9TC GHRAo/ICBrx9izoCtbN+2rj5nO5kZujf8CrnAy19EfonXtP9oQx7lvUdKWn3QPScUiUf h29QDF4S8WrdWWp6idu9toirRGhfckfZyXKgZQEfI3tnmQM2B2LUtqUSflFi5rL2E+HE MW1iz1vxwI/XxA3TqlUGys32pUeDLXqjqJ4JfUu1LY+3sESdO5bWYWfRONXElanmYDej ePtHd2r8BG24QJ5M235yb35BdGcTY+tfQosoxp+K+1o2HPEjOUCPotZ2IiWi/1TZJLPt oSVw== X-Gm-Message-State: ANoB5pnxE58TclhTrtc1QSlx55HiRjFre1HO1HHYdkplZrod3ygrM4VU Jq1Y9JKA4K4Bl3XG70/pjVyPnA== X-Google-Smtp-Source: AA0mqf6acwWia0+L1cEYLvnWvOdyNLyE2K918tcmbn+t7myfCn9EV5mMEmTTmBYN843Wow+kKCJ09g== X-Received: by 2002:a17:902:ec01:b0:186:878e:3b0d with SMTP id l1-20020a170902ec0100b00186878e3b0dmr47042474pld.149.1669898420501; Thu, 01 Dec 2022 04:40:20 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.81.69]) by smtp.gmail.com with ESMTPSA id b65-20020a62cf44000000b0056f0753390csm3246981pfg.96.2022.12.01.04.40.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 04:40:20 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Conor Dooley , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v5 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Date: Thu, 1 Dec 2022 18:09:54 +0530 Message-Id: <20221201123954.1111603-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221201123954.1111603-1-apatel@ventanamicro.com> References: <20221201123954.1111603-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when riscv,timer-cannot-wake-cpu DT property is present in the RISC-V timer DT node. This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device based on RISC-V platform capabilities rather than having it set for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt --- drivers/clocksource/timer-riscv.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 969a552da8d2..1b4b36df5484 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -28,6 +28,7 @@ #include =20 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); +static bool riscv_timer_cannot_wake_cpu; =20 static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) @@ -51,7 +52,7 @@ static int riscv_clock_next_event(unsigned long delta, static unsigned int riscv_clock_event_irq; static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) =3D { .name =3D "riscv_timer_clockevent", - .features =3D CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP, + .features =3D CLOCK_EVT_FEAT_ONESHOT, .rating =3D 100, .set_next_event =3D riscv_clock_next_event, }; @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) =20 ce->cpumask =3D cpumask_of(cpu); ce->irq =3D riscv_clock_event_irq; + if (riscv_timer_cannot_wake_cpu) + ce->features |=3D CLOCK_EVT_FEAT_C3STOP; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); =20 enable_percpu_irq(riscv_clock_event_irq, @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_no= de *n) if (cpuid !=3D smp_processor_id()) return 0; =20 + child =3D of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu =3D of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + domain =3D NULL; child =3D of_get_compatible_child(n, "riscv,cpu-intc"); if (!child) { --=20 2.34.1