From nobody Fri Sep 19 00:54:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4714AC47088 for ; Wed, 30 Nov 2022 22:57:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229675AbiK3W5P (ORCPT ); Wed, 30 Nov 2022 17:57:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229514AbiK3W5M (ORCPT ); Wed, 30 Nov 2022 17:57:12 -0500 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B97192A0A; Wed, 30 Nov 2022 14:57:09 -0800 (PST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4NMvjD3ktTz4xGM; Thu, 1 Dec 2022 09:57:04 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canb.auug.org.au; s=201702; t=1669849025; bh=lH3ZdNsbzBDqZQvPGPjYU5CgMs8PuJgaZZ7rFv3jwkY=; h=Date:From:To:Cc:Subject:From; b=dPhWv0FYg+1/xZLFLgSXaQDwgo7cEg9x/dRCSwEVx7gVbMk2Cpwx36VExiqtLvz+N l6Ncul0o4h0Ekk9S0/Qnne+YlEy4b+sG+chOKvsJ8y95cRg6RFfBLhnD2u7cE00vFC KChZxC+sbFwRBwAsm9bYhUBxRBwI7W58jkthMUz7tTwkGGrByD1VCOlrxKztTxsD6G QvcNU+qKTizVa8Xbk5h8RWRaUbdiCX7SI1WbW0QYCry00F2CrMXfU5h9KNJxVOF0Pb WfFfdf+i7i26kw+67Ru2ZjPeny7h43IVV0czp82qnDqnO8Vp/JPyaoJ+kHdVGCogX7 HWAIwX2rsrfjg== Date: Thu, 1 Dec 2022 09:57:00 +1100 From: Stephen Rothwell To: Dave Airlie , DRI Cc: Andrzej Hajda , Linus Torvalds , Linux Kernel Mailing List , Linux Next Mailing List , Matt Roper Subject: linux-next: manual merge of the drm tree with Linus' tree Message-ID: <20221201095700.7325e73a@canb.auug.org.au> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/oxECwUXRyVqokrbyUg1Ffx."; protocol="application/pgp-signature"; micalg=pgp-sha256 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Sig_/oxECwUXRyVqokrbyUg1Ffx. Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Hi all, Today's linux-next merge of the drm tree got a conflict in: drivers/gpu/drm/i915/gt/intel_gt.c between commit: 04aa64375f48 ("drm/i915: fix TLB invalidation for Gen12 video and compute= engines") from Linus' tree and commit: 46c507f03a46 ("drm/i915/gt: Always use MCR functions on multicast registe= rs") from the drm tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. --=20 Cheers, Stephen Rothwell diff --cc drivers/gpu/drm/i915/gt/intel_gt.c index 7caa3412a244,0325f071046c..000000000000 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@@ -1018,16 -1103,17 +1108,22 @@@ static void mmio_invalidate_full(struc if (!intel_engine_pm_is_awake(engine)) continue; =20 - rb =3D get_reg_and_bit(engine, regs =3D=3D gen8_regs, regs, num); - if (!i915_mmio_reg_offset(rb.reg)) - continue; -=20 - if (GRAPHICS_VER(i915) =3D=3D 12 && (engine->class =3D=3D VIDEO_DECODE_= CLASS || - engine->class =3D=3D VIDEO_ENHANCEMENT_CLASS || - engine->class =3D=3D COMPUTE_CLASS)) - rb.bit =3D _MASKED_BIT_ENABLE(rb.bit); -=20 - intel_uncore_write_fw(uncore, rb.reg, rb.bit); + if (GRAPHICS_VER_FULL(i915) >=3D IP_VER(12, 50)) { + intel_gt_mcr_multicast_write_fw(gt, + xehp_regs[engine->class], + BIT(engine->instance)); + } else { + rb =3D get_reg_and_bit(engine, regs =3D=3D gen8_regs, regs, num); + if (!i915_mmio_reg_offset(rb.reg)) + continue; +=20 ++ if (GRAPHICS_VER(i915) =3D=3D 12 && (engine->class =3D=3D VIDEO_DECODE= _CLASS || ++ engine->class =3D=3D VIDEO_ENHANCEMENT_CLASS || ++ engine->class =3D=3D COMPUTE_CLASS)) ++ rb.bit =3D _MASKED_BIT_ENABLE(rb.bit); ++ + intel_uncore_write_fw(uncore, rb.reg, rb.bit); + } awake |=3D engine->mask; } =20 --Sig_/oxECwUXRyVqokrbyUg1Ffx. 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