From nobody Sat Sep 21 07:38:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ACAFC4321E for ; Thu, 1 Dec 2022 08:42:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229770AbiLAImo (ORCPT ); Thu, 1 Dec 2022 03:42:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229747AbiLAImj (ORCPT ); Thu, 1 Dec 2022 03:42:39 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 280F260C8 for ; Thu, 1 Dec 2022 00:42:37 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id f9so1068138pgf.7 for ; Thu, 01 Dec 2022 00:42:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/sbFnIzF7qvR5A534InqCHDBcQlt3cOWkJpUNrDM5kY=; b=XDENRWACJueRJJLfr0sZFDJNEVniluetT+EiqOGJ2elV26Aly+mIXeq2OITr5R9kxX axPog3rAomaLwvpSkndt+RwSLx2DEPNBuTXQRA38Q0TNG0wjPk9RLElkHAwIgUPgZ+ad hJxEa3TL9a97p3SZ8flTXNyyFpZ+zkV7xN/Tc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/sbFnIzF7qvR5A534InqCHDBcQlt3cOWkJpUNrDM5kY=; b=sDcJNb+NkVdl9Fdhrn1pVKGa0UP3GyM5JY8jUuGfuPUiGKWrc2JkQ1jG9NRcYTcDha qMt6XuXFCdmX5X+XPg9c3pQ4zuzw9PfdkMSuKAKom78vT//5JWEf6ObdkZsf91pC6pw/ BdTYiG/kRxQwE3SR3Yp6gxT5jc13WwtDrum/6roqdM7ZoFr+WW6g2bMv3ZUQQaXexXrP HZ8spI+CTVBw4Hnrh80Z9R/ych8GpdZ4r6pfMiXOjxEVXqa/dMGTZiMNfXmI6FyWGenW 9jHKMMK90Y2hwKY9YpC0h5977H5MMgVuDTIXIfc1yNa8mGeuVo35SQdweEdEpEp7q/K8 Pu0A== X-Gm-Message-State: ANoB5plBOHkrGDtpCTSMB2MoGGCVPpsU45hTq6lWtfBwGpi4XyIGKwTz 2PsDS5w8284Sw4b7OPU038XrGg== X-Google-Smtp-Source: AA0mqf5rTcAjwUigYrgSRA+tffO2tIneJKwa7IosCaE5clajLMjwbQEUOGwXTJG+yg8z36bdvgBRbw== X-Received: by 2002:a63:f962:0:b0:477:1bb8:bbf4 with SMTP id q34-20020a63f962000000b004771bb8bbf4mr40359999pgk.19.1669884156715; Thu, 01 Dec 2022 00:42:36 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:2416:fa4e:4eeb:fcde]) by smtp.gmail.com with ESMTPSA id j5-20020a170902690500b001708c4ebbaesm2932293plk.309.2022.12.01.00.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 00:42:36 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH 1/4] arm64: dts: mediatek: mt8183: Fix systimer 13 MHz clock description Date: Thu, 1 Dec 2022 16:42:26 +0800 Message-Id: <20221201084229.3464449-2-wenst@chromium.org> X-Mailer: git-send-email 2.38.1.584.g0f3c55d4c2-goog In-Reply-To: <20221201084229.3464449-1-wenst@chromium.org> References: <20221201084229.3464449-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8183 this divider is set either by power-on-reset or by the bootloader. The bootloader may then make the divider unconfigurable to, but can be read out by, the operating system. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 5bc8e2875ffb ("arm64: dts: mt8183: add systimer0 device node") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 19ff1babc359..0cbbaebe1213 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -585,6 +585,15 @@ psci { method =3D "smc"; }; =20 + clk13m: fixed-factor-clock-13m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "clk13m"; + }; + clk26m: oscillator { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -968,8 +977,7 @@ systimer: timer@10017000 { "mediatek,mt6765-timer"; reg =3D <0 0x10017000 0 0x1000>; interrupts =3D ; - clocks =3D <&topckgen CLK_TOP_CLK13M>; - clock-names =3D "clk13m"; + clocks =3D <&clk13m>; }; =20 iommu: iommu@10205000 { --=20 2.38.1.584.g0f3c55d4c2-goog From nobody Sat Sep 21 07:38:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17664C4708C for ; Thu, 1 Dec 2022 08:42:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229756AbiLAIms (ORCPT ); Thu, 1 Dec 2022 03:42:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229757AbiLAImm (ORCPT ); Thu, 1 Dec 2022 03:42:42 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AABBDFC6 for ; Thu, 1 Dec 2022 00:42:39 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id k5so1211706pjo.5 for ; Thu, 01 Dec 2022 00:42:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/WOeFuUzcolWHnZuc7pdP9VxPOXM1oDwP4XAacQirfk=; b=Db38O9+lHRZcLVg6Gbmwkz4xrvTz6HETUHmq8LkST7DxaWmHW8hiFgaJcnDpokbDcd HkWqdpu6rZKau4iS4Tj0gu2ffXPotKHe3uk3GmiiO7OK+GCSwDXx1EqCZ5ZovhHk8GSU HIsmrI4RclhucCrtNGW8OWPxuNtI3F4nE08vY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/WOeFuUzcolWHnZuc7pdP9VxPOXM1oDwP4XAacQirfk=; b=1myAal/R/6YizVFgQZ2srWHEc7vvof+PDICzWT6s3ORA0kk6Vt/hR3O5LoZ1U3uxSz 41canCLPsitP1v6vQ2H/dqatW6UQxMi+E3V6fVhbGcbStdRhMICWIJAVZuesuxFpuES2 n/FhJDcyRpSU9+PtQZcczB8pr/4mPBfCIlFclgkprn4yjtrK2KchmJCNphK6hMY1JwB0 kUS6zWdFkkPEaDynBqWbKIg9c+qZeEQWOMJmMgB2Tu8O8AqVFFA65h3Cn+BWVPGf7Oi8 WKUf28gbdIpw26UPOZM4usul76h6NyMdYZnJTCMuNuiG+Csb2MeqrNYORyGRPJcaDmYA 9R2g== X-Gm-Message-State: ANoB5pnyG0/bpBAv8iqG9OD2JWbu2h4pW8E/01sCcKSYNc243cjvdRy8 SgWsuZJ5DJMOzhzDkm4dFfgeVA== X-Google-Smtp-Source: AA0mqf41cigCeKSKmoN4bvphHgVPZ/wH2bU7xeJPntvphumOR1EcxVdeLfSSCX1ZL+sef2jSk8zT0g== X-Received: by 2002:a17:903:4051:b0:170:f343:ba14 with SMTP id n17-20020a170903405100b00170f343ba14mr46469201pla.70.1669884159302; Thu, 01 Dec 2022 00:42:39 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:2416:fa4e:4eeb:fcde]) by smtp.gmail.com with ESMTPSA id j5-20020a170902690500b001708c4ebbaesm2932293plk.309.2022.12.01.00.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 00:42:38 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH 2/4] arm64: dts: mediatek: mt8192: Fix systimer 13 MHz clock description Date: Thu, 1 Dec 2022 16:42:27 +0800 Message-Id: <20221201084229.3464449-3-wenst@chromium.org> X-Mailer: git-send-email 2.38.1.584.g0f3c55d4c2-goog In-Reply-To: <20221201084229.3464449-1-wenst@chromium.org> References: <20221201084229.3464449-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8192 this divider is fixed to /2 and is not configurable. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation bo= ard dts and Makefile") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index fc39ccc0d4bf..ab4d4f605493 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -29,6 +29,15 @@ aliases { rdma4 =3D &rdma4; }; =20 + clk13m: fixed-factor-clock-13m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "clk13m"; + }; + clk26m: oscillator0 { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -534,8 +543,7 @@ systimer: timer@10017000 { "mediatek,mt6765-timer"; reg =3D <0 0x10017000 0 0x1000>; interrupts =3D ; - clocks =3D <&topckgen CLK_TOP_CSW_F26M_D2>; - clock-names =3D "clk13m"; + clocks =3D <&clk13m>; }; =20 pwrap: pwrap@10026000 { --=20 2.38.1.584.g0f3c55d4c2-goog From nobody Sat Sep 21 07:38:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAF9FC43217 for ; Thu, 1 Dec 2022 08:42:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229571AbiLAImv (ORCPT ); Thu, 1 Dec 2022 03:42:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229773AbiLAImo (ORCPT ); Thu, 1 Dec 2022 03:42:44 -0500 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58BD72BC3 for ; Thu, 1 Dec 2022 00:42:42 -0800 (PST) Received: by mail-pg1-x534.google.com with SMTP id q1so1055515pgl.11 for ; Thu, 01 Dec 2022 00:42:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pEDSSsGGM8AAJ08Auy3dp0LttRqfjGQgPHRv4DynzpI=; b=JHG3IJ5JSznG6iCGYmm3FiA0E7POVkCHlHG7XLvYJlBlS8s4Ba6MxkQ6SeLKll4P9l ccNoLbhVbNntAuDvg+izoM0R3lAP89T5vwxqu97HmlQ/7dTSiDe7Um1JCRJCC8bohxjn cnEn91GHN9Ac1Iio8VqHyRJc+wFgln0Zwh40M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pEDSSsGGM8AAJ08Auy3dp0LttRqfjGQgPHRv4DynzpI=; b=xlk/vE80iMc3XScuT+cEPNqbk91MRr/vXNwjlbJz+e0D6pbVGTpa6SZNFsSr4klcbo p6nTcmp6uKpp06eZG8qwdORfFD++dyUKsR9pAnh0+yY+SW/b3fKqwgBCL/qFTz//Ba23 pTh5/JTrUlnmvcAI5vntmRkBCD+XT7kxgCmbfdasZZ55z3CwRh1jsN5VQDveOqFQzxQ+ EUf4J6jMsxGunthmnKsCnILGPI5SJngPsElp3NoAo/cwqEOIPwS9ueuDYDP9puPIGdaQ 255ufpI1oXaOxo+RoEInGJdyCCISgo04JJzLT4n/lH840d3uhDpqoWwPdyl1aGXrTKsu Fztw== X-Gm-Message-State: ANoB5pm7DfyAJ4Ti8Z8kIdhbr+Fq3OGwI6213iz6JqWINAqXMsaDXXoh KaKuwrHYiC07MJp1ZnFbgZh4iA== X-Google-Smtp-Source: AA0mqf7FyYTwcmw9tGrsj+b4l/tHPqvoUEIpnviYSG3/NSB7K4eKIhAfRVx7XgZPfbPoxY9gp0nx0g== X-Received: by 2002:a63:da10:0:b0:477:ccac:6eb5 with SMTP id c16-20020a63da10000000b00477ccac6eb5mr30861853pgh.41.1669884161760; Thu, 01 Dec 2022 00:42:41 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:2416:fa4e:4eeb:fcde]) by smtp.gmail.com with ESMTPSA id j5-20020a170902690500b001708c4ebbaesm2932293plk.309.2022.12.01.00.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 00:42:41 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH 3/4] arm64: dts: mediatek: mt8195: Fix systimer 13 MHz clock description Date: Thu, 1 Dec 2022 16:42:28 +0800 Message-Id: <20221201084229.3464449-4-wenst@chromium.org> X-Mailer: git-send-email 2.38.1.584.g0f3c55d4c2-goog In-Reply-To: <20221201084229.3464449-1-wenst@chromium.org> References: <20221201084229.3464449-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8195 this divider is set either by power-on-reset or by the bootloader. The bootloader may then make the divider unconfigurable to, but can be read out by, the operating system. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation bo= ard") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 5d31536f4c48..60e15833956e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -248,6 +248,15 @@ sound: mt8195-sound { status =3D "disabled"; }; =20 + clk13m: fixed-factor-clock-13m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "clk13m"; + }; + clk26m: oscillator-26m { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -705,7 +714,7 @@ systimer: timer@10017000 { "mediatek,mt6765-timer"; reg =3D <0 0x10017000 0 0x1000>; interrupts =3D ; - clocks =3D <&topckgen CLK_TOP_CLK26M_D2>; + clocks =3D <&clk13m>; }; =20 pwrap: pwrap@10024000 { --=20 2.38.1.584.g0f3c55d4c2-goog From nobody Sat Sep 21 07:38:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A30D0C43217 for ; Thu, 1 Dec 2022 08:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229776AbiLAInB (ORCPT ); Thu, 1 Dec 2022 03:43:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229782AbiLAImr (ORCPT ); Thu, 1 Dec 2022 03:42:47 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 138F01DA73 for ; Thu, 1 Dec 2022 00:42:44 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id k7so995970pll.6 for ; Thu, 01 Dec 2022 00:42:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V298lkV5QtI9GGd+VqJ9vB4qdc38PxeAIxTF+s8oIPU=; b=HXNerBkWxszjzmqR+65CvsTOErf+iOTLkDjru19S6a7Uz08AbN/rnneQjLsuIJvrwr Dg4WpD9aZ6NDY+2mQzKl90XlI6RelVXlXhdV3g6eI1GbO5rHFK0JkQSA/Uh9EvY/A0St ykQNoytvUS9qE6UxB7Ts+ItS8hkq2vLt19GbE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V298lkV5QtI9GGd+VqJ9vB4qdc38PxeAIxTF+s8oIPU=; b=ayTQ4s/nPVp5xMrYJTJWwU82NYt0EdN39aW1FPrQOGJavxkbJhIyiAsik41kbfDGbb sNvCcT6wcIbBSYtHz7XMMp7KwTmrsF6AOKZLwtofI7MBTbOVeu49IsT4Hb03RD4LTjVE FAeHG6PFh0+IwCNZlXwMo0YKooff8GXhM42uxC4H8ssoINifEngeME8sb2RguCsGgbIw r3dSCeaILe3pjjXXrnjo7S99kd9fsQbHPZpqgKe6uAAXThNqDkonCNCIke8Gh4WZHsIF g2EJSsJ5OY5J4qt1ZrUOdki0HiZ8OHXPPow7fjSZOQac/6svvQL3IOPj6bwGob6p7ITs CF+g== X-Gm-Message-State: ANoB5pkzl3ou7Ii1Bl22iawj4HYWDGi2rDWmWconyu0RQUhfvnQVGluQ GS6KVj9uJSvngHtZQ33Envju1w== X-Google-Smtp-Source: AA0mqf665+1a7uoBaUKEuv2A7tuu9y7S3ALImhvKQOwgh7iwjPQZ077I2pm6cCd4wI2XcxO8yLOpyQ== X-Received: by 2002:a17:90a:4594:b0:218:f745:76fe with SMTP id v20-20020a17090a459400b00218f74576femr37452609pjg.245.1669884163980; Thu, 01 Dec 2022 00:42:43 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:2416:fa4e:4eeb:fcde]) by smtp.gmail.com with ESMTPSA id j5-20020a170902690500b001708c4ebbaesm2932293plk.309.2022.12.01.00.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 00:42:43 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH 4/4] arm64: dts: mediatek: mt8186: Fix systimer 13 MHz clock description Date: Thu, 1 Dec 2022 16:42:29 +0800 Message-Id: <20221201084229.3464449-5-wenst@chromium.org> X-Mailer: git-send-email 2.38.1.584.g0f3c55d4c2-goog In-Reply-To: <20221201084229.3464449-1-wenst@chromium.org> References: <20221201084229.3464449-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally. The 13 MHz clock is not a separate oscillator. Fix this by making the 13 MHz clock a divide-by-2 fixed factor clock, taking its input from the main 26 MHz oscillator. Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation bo= ard and Makefile") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 4a2f7ad3c6f0..209f26f12dbc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -215,10 +215,12 @@ l3_0: l3-cache { }; }; =20 - clk13m: oscillator-13m { - compatible =3D "fixed-clock"; + clk13m: fixed-factor-clock-13m { + compatible =3D "fixed-factor-clock"; #clock-cells =3D <0>; - clock-frequency =3D <13000000>; + clocks =3D <&clk26m>; + clock-div =3D <2>; + clock-mult =3D <1>; clock-output-names =3D "clk13m"; }; =20 --=20 2.38.1.584.g0f3c55d4c2-goog