From nobody Sat Sep 21 08:43:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32659C47088 for ; Thu, 1 Dec 2022 07:33:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229815AbiLAHds (ORCPT ); Thu, 1 Dec 2022 02:33:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229910AbiLAHdn (ORCPT ); Thu, 1 Dec 2022 02:33:43 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2A3132047; Wed, 30 Nov 2022 23:33:39 -0800 (PST) X-UUID: f60f3869cfd94774a36a8475ca396d66-20221201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=GEB/PItp3ApqYqJMuq7w9mwjWCEXCCq4x+XaxUYFjtY=; b=WGLBy8dU39blEpJFwRgIQVMqlq4N5GUMWE1ApWNtuEa8bXgFJQoA7bL1IRonaCvyP82UYVWL6uzzL1YReIcNm6egKUOvDfQdF+shpxJLwppxqpvMzE4AELDazkxkX2DAqvN9pnMY7mJHi7v9yY01fdUnU5SyBfllwVgcz4bJDG8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:9389cffb-4fcc-4b91-9c5f-ebd33effa78c,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:9389cffb-4fcc-4b91-9c5f-ebd33effa78c,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:68a23e6c-41fe-47b6-8eb4-ec192dedaf7d,B ulkID:221201153334SA4JXALR,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f60f3869cfd94774a36a8475ca396d66-20221201 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1360004168; Thu, 01 Dec 2022 15:33:32 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 1 Dec 2022 15:33:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 1 Dec 2022 15:33:30 +0800 From: Allen-KH Cheng To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH] arm64: dts: mt8192: Add adsp power domain controller Date: Thu, 1 Dec 2022 15:33:28 +0800 Message-ID: <20221201073328.1559-1-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add adsp power domain controller node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- Ref: https://lore.kernel.org/all/2ec80bd8-dfef-d2e6-eb41-6e6088043e33@colla= bora.com/ [Allen-KH Cheng ] --- --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 8 ++++++++ include/dt-bindings/power/mt8192-power.h | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 424fc89cc6f7..e71afba871fc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -514,6 +514,14 @@ }; }; }; + + power-domain@MT8192_POWER_DOMAIN_ADSP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_ADSP_SEL>; + clock-names =3D "adsp"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; }; }; =20 diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings= /power/mt8192-power.h index 4eaa53d7270a..63e81cd0d06d 100644 --- a/include/dt-bindings/power/mt8192-power.h +++ b/include/dt-bindings/power/mt8192-power.h @@ -28,5 +28,6 @@ #define MT8192_POWER_DOMAIN_CAM_RAWA 18 #define MT8192_POWER_DOMAIN_CAM_RAWB 19 #define MT8192_POWER_DOMAIN_CAM_RAWC 20 +#define MT8192_POWER_DOMAIN_ADSP 21 =20 #endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ --=20 2.18.0