From nobody Fri Sep 19 02:17:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22553C433FE for ; Wed, 30 Nov 2022 11:29:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232131AbiK3L3c (ORCPT ); Wed, 30 Nov 2022 06:29:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229457AbiK3L3U (ORCPT ); Wed, 30 Nov 2022 06:29:20 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABD0C10FFA for ; Wed, 30 Nov 2022 03:29:18 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id td2so26464790ejc.5 for ; Wed, 30 Nov 2022 03:29:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rbpQaf4g+r4gt9AxpFOseMq1ZYh9Lq0nCyM5eOF1Zm8=; b=djdyFg8ldNxDjJLVlAxmIpIXm1fVQ4yaKrIAHEIVQKRFYPrtxJuYwjpdUtIPGPfKMR N64I+SJJJqwoWuGTWn4OR8oBGarBEDZ1AQEVLjvV6JBfDP5S3Npjj4ey1kl3xj9ylsTJ 2ciS7HB9RFkyInlhrTy9liMj7EJ9HooSLeTELhM/YbLzo0gJvHlcjQa9R0koWXj8YiEu 3MivVtC8X7alBueGsiUyQlaJSxKVDqQu0+eNusAb+scNM2Dv+lN55N/TuXLrpWcVJ4SQ 9/0WfImFrgwMUC9kix6Nz2af9YZ0l0ZjTsDl0aRmqULkSKhqAzPoFuFSz2gre6RX+nSy yAeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rbpQaf4g+r4gt9AxpFOseMq1ZYh9Lq0nCyM5eOF1Zm8=; b=XFntEY6WepQeOgEqGxEUqiBE/feup3xntSiUkCrY0+R5F507srLHvfKhyhcxAi9t/y JEgdoy0nzLwsArmnydmKQ6U5qBN7f0TGvvdi/pmvQbxL/LZfbsfwCtGVEzJJnnxjlDOX O2uL9nUBrnHWqzk4SwDFVqFCKCA1TmcFn2ZVdEwMZe8qYmiCTwWMehJYxG6FDSEdEdmc 9PzfEVCFHHbMvHL5zl7ifsIIUaeKlW2KstN053et6jBuhi2Vqu1hX+UqLl+7Jv21/QTC XIQR45j8ShB84pUwDXdm2lFk57mPuQwOmvrCTOZBUWqG/fZVcU4nwq4AVg+57Cd4bYqM yGlA== X-Gm-Message-State: ANoB5pluUlwO4D7e2ED08rCNEQTRuNDXHb0xV36uLgxRMurTKgWGcM9e hW+CjMumXHM/0KMqtwGCRb33NA== X-Google-Smtp-Source: AA0mqf4QUeFq+uy491MEOyOBxjO9ZGN7xPAoRi/DfXddjJ7wV9wxfWjHWaIfuoHW3tuAT56Y6MK8Ng== X-Received: by 2002:a17:906:7119:b0:7c0:a181:90c7 with SMTP id x25-20020a170906711900b007c0a18190c7mr1430401ejj.632.1669807757283; Wed, 30 Nov 2022 03:29:17 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id x10-20020a1709060a4a00b007c073be0127sm521593ejf.202.2022.11.30.03.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 03:29:16 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 2/9] dt-bindings: clock: Add SM8550 TCSR CC clocks Date: Wed, 30 Nov 2022 13:28:45 +0200 Message-Id: <20221130112852.2977816-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221130112852.2977816-1-abel.vesa@linaro.org> References: <20221130112852.2977816-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsrcc.yaml | 45 +++++++++++++++++++ .../dt-bindings/clock/qcom,sm8550-tcsrcc.h | 18 ++++++++ 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcs= rcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsrcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsrcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsrcc.yaml new file mode 100644 index 000000000000..b2de251328e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsrcc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsrcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsrcc.h + +properties: + compatible: + const: qcom,sm8550-tcsrcc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + clock-controller@1fc0000 { + compatible =3D "qcom,sm8550-tcsrcc"; + reg =3D <0x1fc0000 0x30000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsrcc.h b/include/dt-bi= ndings/clock/qcom,sm8550-tcsrcc.h new file mode 100644 index 000000000000..091cb76f953a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-tcsrcc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif --=20 2.34.1