From nobody Fri Sep 19 03:43:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8755C4332F for ; Tue, 29 Nov 2022 21:09:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236822AbiK2VJS (ORCPT ); Tue, 29 Nov 2022 16:09:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236761AbiK2VJF (ORCPT ); Tue, 29 Nov 2022 16:09:05 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F04B8116E for ; Tue, 29 Nov 2022 13:09:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756143; x=1701292143; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=niny0WNbiHjtWmixHGOged4GvvPKSLIrCEDitMSqwFg=; b=FNGLCYj4i35hwjjS1y6iTxBpIlA1agriDPHy8G085RPdNfJAa+sjV3gJ P3r+dyqGc/ted7IUccgk4LpdFB9kFI8YvC0YtVuaR4L4elTVFBqZ8duLw g/49BmxDFks4QNYHKpwsuMHIGeu8ehaCTTLrFeV5Lo98qhM4d3SRWw4AX Xf9Yb/csGF50Xn0s+663RGV0dF6rQgg4+GTmji2RlpOwjJ3QdGcs7hQHs 0KxE55Inkp8NDjDaiyDQUIJTluZ6xqeXxly7GEoPeRVcwzmnV+om+eYPG t4VHr/JKKhH91EVI4CV9cHY7W+9Ftc3izQko18oNq+eJNLo3S6MqKfCi9 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083127" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083127" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:03 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066201" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066201" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:03 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 1/7] x86/microcode/intel: Remove redundant microcode rev pr_info()s Date: Tue, 29 Nov 2022 13:08:26 -0800 Message-Id: <20221129210832.107850-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is a pr_info() to dump information about newly loaded microcode. The code intends this pr_info() to be just once, but the check to ensure is racy. Unfortunately this happens quite often in with this new change resulting in multiple redundant prints on the console. microcode_init()->schedule_on_each_cpu(setup_online_cpu)->collect_cpu_info [ 33.688639] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 [ 33.688659] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 [ 33.688660] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 There is already a pr_info() in microcode/core.c as shown below: microcode: Reload completed, microcode revision: 0x2b000041 -> 0x2b000070 The sig and pf aren't that useful to end user, they are available via /proc/cpuinfo and this never changes between microcode loads. Remove the redundant pr_info() and the racy single print checks. This removes the race entirely, zap the duplicated pr_info() spam and simplify the code. Fixes: b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") Reported-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index c4a00fb97f61..4f93875f57b4 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -554,7 +554,6 @@ void reload_ucode_intel(void) =20 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { - static struct cpu_signature prev; struct cpuinfo_x86 *c =3D &cpu_data(cpu_num); unsigned int val[2]; =20 @@ -570,13 +569,6 @@ static int collect_cpu_info(int cpu_num, struct cpu_si= gnature *csig) =20 csig->rev =3D c->microcode; =20 - /* No extra locking on prev, races are harmless. */ - if (csig->sig !=3D prev.sig || csig->pf !=3D prev.pf || csig->rev !=3D pr= ev.rev) { - pr_info("sig=3D0x%x, pf=3D0x%x, revision=3D0x%x\n", - csig->sig, csig->pf, csig->rev); - prev =3D *csig; - } - return 0; } =20 --=20 2.34.1