From nobody Fri Sep 19 02:17:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8755C4332F for ; Tue, 29 Nov 2022 21:09:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236822AbiK2VJS (ORCPT ); Tue, 29 Nov 2022 16:09:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236761AbiK2VJF (ORCPT ); Tue, 29 Nov 2022 16:09:05 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F04B8116E for ; Tue, 29 Nov 2022 13:09:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756143; x=1701292143; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=niny0WNbiHjtWmixHGOged4GvvPKSLIrCEDitMSqwFg=; b=FNGLCYj4i35hwjjS1y6iTxBpIlA1agriDPHy8G085RPdNfJAa+sjV3gJ P3r+dyqGc/ted7IUccgk4LpdFB9kFI8YvC0YtVuaR4L4elTVFBqZ8duLw g/49BmxDFks4QNYHKpwsuMHIGeu8ehaCTTLrFeV5Lo98qhM4d3SRWw4AX Xf9Yb/csGF50Xn0s+663RGV0dF6rQgg4+GTmji2RlpOwjJ3QdGcs7hQHs 0KxE55Inkp8NDjDaiyDQUIJTluZ6xqeXxly7GEoPeRVcwzmnV+om+eYPG t4VHr/JKKhH91EVI4CV9cHY7W+9Ftc3izQko18oNq+eJNLo3S6MqKfCi9 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083127" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083127" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:03 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066201" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066201" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:03 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 1/7] x86/microcode/intel: Remove redundant microcode rev pr_info()s Date: Tue, 29 Nov 2022 13:08:26 -0800 Message-Id: <20221129210832.107850-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is a pr_info() to dump information about newly loaded microcode. The code intends this pr_info() to be just once, but the check to ensure is racy. Unfortunately this happens quite often in with this new change resulting in multiple redundant prints on the console. microcode_init()->schedule_on_each_cpu(setup_online_cpu)->collect_cpu_info [ 33.688639] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 [ 33.688659] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 [ 33.688660] microcode: sig=3D0x50654, pf=3D0x80, revision=3D0x2006e05 There is already a pr_info() in microcode/core.c as shown below: microcode: Reload completed, microcode revision: 0x2b000041 -> 0x2b000070 The sig and pf aren't that useful to end user, they are available via /proc/cpuinfo and this never changes between microcode loads. Remove the redundant pr_info() and the racy single print checks. This removes the race entirely, zap the duplicated pr_info() spam and simplify the code. Fixes: b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") Reported-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index c4a00fb97f61..4f93875f57b4 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -554,7 +554,6 @@ void reload_ucode_intel(void) =20 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { - static struct cpu_signature prev; struct cpuinfo_x86 *c =3D &cpu_data(cpu_num); unsigned int val[2]; =20 @@ -570,13 +569,6 @@ static int collect_cpu_info(int cpu_num, struct cpu_si= gnature *csig) =20 csig->rev =3D c->microcode; =20 - /* No extra locking on prev, races are harmless. */ - if (csig->sig !=3D prev.sig || csig->pf !=3D prev.pf || csig->rev !=3D pr= ev.rev) { - pr_info("sig=3D0x%x, pf=3D0x%x, revision=3D0x%x\n", - csig->sig, csig->pf, csig->rev); - prev =3D *csig; - } - return 0; } =20 --=20 2.34.1 From nobody Fri Sep 19 02:17:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38719C433FE for ; Tue, 29 Nov 2022 21:09:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236825AbiK2VJX (ORCPT ); Tue, 29 Nov 2022 16:09:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236084AbiK2VJG (ORCPT ); Tue, 29 Nov 2022 16:09:06 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7919F55A0 for ; Tue, 29 Nov 2022 13:09:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756144; x=1701292144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CQp4qbII0DlxhRkqqCYEfCUWHdc6N9otPMAR1s7O/AM=; b=TY4QdO1TM6rxlpJvouVXEdRgnA/UyPI1zFZCbd17oChagrx9LnKEI4+E lJIvy7TrR0GpwxiMolddOJnTQ+Dhd/haAHRvG0jpqldFvtkLXZDSvSy4H LsrHNPpaRAFVN1Tn2Gud0+N+VGI9zxxLUVNrfuT1mwhSbIqFWb5/QwZe5 BKD2OmNKM7IoTVcu4fH+k2+rUb6NknL0tPZkpnfRb7wRABSnZ/aLVM/oj Y2SH1cmJBGNIa8HqwzTXDEjUt99mT6shePwY+4IeX9hDAOcOWD3tVG7DJ SMX9T3Ri7/XUfo+wUquFOL/40HjsFNsQjLPonNbfF/KbT3+YD/LF4MMfo w==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083131" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083131" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:04 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066205" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066205" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:03 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 2/7] x86/microcode/intel: Remove retries on early microcode load Date: Tue, 29 Nov 2022 13:08:27 -0800 Message-Id: <20221129210832.107850-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Microcode loading can fail. This happens today when handling mixed steppings. But it can also happen for other reasons such as corrupted image, Security Version Number (SVN) preventing anti-rollback, dependencies on BIOS loaded microcode image for some capabilities. When the microcode loading fails, the kernel will quietly hang at boot. This has been observed by end users (Links below) who had to revert their microcode packages in order to boot again. The hang is due to an infinite retry loop. The retries were in place to support systems with mixed steppings. Now that mixed steppings are no longer supported, there is only one microcode image at a time. Any retries will simply reattempt to apply the same image over and over without making progress. Some possible past bugs that could be due to this bug are below. There is no direct evidence that these end user issues were caused by this retry loop. However, the early boot hangs along with reverting the microcode update workaround provide strong circumstantial evidence to support the theory that they are linked. Remove the retry loop and only attempt to apply microcode once. Link: https://bugs.launchpad.net/ubuntu/+source/intel-microcode/+bug/1911959 Link: https://forums.linuxmint.com/viewtopic.php?p=3D1827032#1827032 Link: https://askubuntu.com/questions/1291486/boot-crash-after-latest-updat= e-of-intel-microcode-nov-11-2020 Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Cc: stable@vger.kernel.org Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 4f93875f57b4..d68b084a17e7 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -495,7 +495,6 @@ void load_ucode_intel_ap(void) else iup =3D &intel_ucode_patch; =20 -reget: if (!*iup) { patch =3D __load_ucode_intel(&uci); if (!patch) @@ -505,13 +504,7 @@ void load_ucode_intel_ap(void) } =20 uci.mc =3D *iup; - - if (apply_microcode_early(&uci, true)) { - /* Mixed-silicon system? Try to refetch the proper patch: */ - *iup =3D NULL; - - goto reget; - } + apply_microcode_early(&uci, true); } =20 static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) --=20 2.34.1 From nobody Fri Sep 19 02:17:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC287C433FE for ; Tue, 29 Nov 2022 21:09:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236761AbiK2VJd (ORCPT ); Tue, 29 Nov 2022 16:09:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236741AbiK2VJG (ORCPT ); Tue, 29 Nov 2022 16:09:06 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4233E63CE for ; Tue, 29 Nov 2022 13:09:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756145; x=1701292145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=70gwJLJLXs2AZIFAvJaft9GRLf9mjU7YlemJkv6J9xI=; b=cTLMGliBoVKRr8h8wPJMK6afJnp3psQ5cnPAQPqMHQmBEaxBBC0WVPQv +pf0UOsjJ4ARnfVsRstQDNwrszRIIGypF+5BrgTBdvvFZmcCf/yOkR8fv 0y23bo9a/j9pIcgjBRXLtI9NPM24QYhZd9srk+yUaiSld8b7tgISXR0z6 yH0nCBLebd6VzNA2dLR+uEZsaDHnDRNDa7d/dBfAzlTYaazpgHlxAmpqf YzZQ8gWiGQc7CignNfCrr8xGHKI5H4Qhwf0da39CU6ubUbjVOUFPLWg2E X3zmp/MirquVkEWg2cCj0l011bR2+8WKwd3NC58zgYDn9HyqDK4SzEJpr w==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083136" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083136" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:04 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066208" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066208" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:04 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 3/7] x86/microcode/core: Move microcode_check() to cpu/microcode/core.c Date: Tue, 29 Nov 2022 13:08:28 -0800 Message-Id: <20221129210832.107850-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" microcode_check() is only called from microcode/core.c. Move it and make it static to prepare for upcoming fix of false negative when checking CPU features after a microcode update. Also move get_cpu_cap() to processor.h for general use outside of kernel/cpu.h No functional change. Suggested-by: Alison Schofield Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner --- Tony Add movement of get_cpu_cap() to commit log Reinette Avoid including ../cpu.h and move to more general header. Alison Split patch to just move the function before use inside microcode files. --- arch/x86/include/asm/processor.h | 3 +-- arch/x86/kernel/cpu/cpu.h | 1 - arch/x86/kernel/cpu/common.c | 32 ---------------------------- arch/x86/kernel/cpu/microcode/core.c | 31 +++++++++++++++++++++++++++ 4 files changed, 32 insertions(+), 35 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 67c9d73b31fa..f5380806f3fa 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -192,8 +192,8 @@ extern const struct seq_operations cpuinfo_op; =20 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) =20 +extern void get_cpu_cap(struct cpuinfo_x86 *c); extern void cpu_detect(struct cpuinfo_x86 *c); - static inline unsigned long long l1tf_pfn_limit(void) { return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); @@ -835,7 +835,6 @@ bool xen_set_default_idle(void); #endif =20 void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); =20 enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 7c9b5893c30a..a142b8d543a3 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -63,7 +63,6 @@ static inline void tsx_ap_init(void) { } =20 extern void init_spectral_chicken(struct cpuinfo_x86 *c); =20 -extern void get_cpu_cap(struct cpuinfo_x86 *c); extern void get_cpu_address_sizes(struct cpuinfo_x86 *c); extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c); extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..bbd362ead043 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2305,38 +2305,6 @@ void cpu_init_secondary(void) } #endif =20 -#ifdef CONFIG_MICROCODE_LATE_LOADING -/* - * The microcode loader calls this upon late microcode load to recheck fea= tures, - * only when microcode has been updated. Caller holds microcode_mutex and = CPU - * hotplug lock. - */ -void microcode_check(void) -{ - struct cpuinfo_x86 info; - - perf_check_microcode(); - - /* Reload CPUID max function as it might've changed. */ - info.cpuid_level =3D cpuid_eax(0); - - /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). - */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x= 86_capability)); - - get_cpu_cap(&info); - - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(i= nfo.x86_capability))) - return; - - pr_warn("x86/CPU: CPU features have changed after loading microcode, but = might not take effect.\n"); - pr_warn("x86/CPU: Please consider either early loading through initrd/bui= lt-in or a potential BIOS update.\n"); -} -#endif - /* * Invoked from core CPU hotplug code after hotplug operations */ diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 712aafff96e0..ef24e1d228d0 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -431,6 +431,37 @@ static int __reload_late(void *info) return ret; } =20 +/* + * The microcode loader calls this upon late microcode load to recheck fea= tures, + * only when microcode has been updated. Caller holds microcode_mutex and = CPU + * hotplug lock. + */ +static void microcode_check(void) +{ + struct cpuinfo_x86 info; + + perf_check_microcode(); + + /* Reload CPUID max function as it might've changed. */ + info.cpuid_level =3D cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x= 86_capability)); + + get_cpu_cap(&info); + + if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, + sizeof(info.x86_capability))) + return; + + pr_warn("x86/CPU: CPU features have changed after loading microcode, but = might not take effect.\n"); + pr_warn("x86/CPU: Please consider either early loading through initrd/bui= lt-in or a potential BIOS update.\n"); +} + /* * Reload microcode late on all CPUs. Wait for a sec until they * all gather together. --=20 2.34.1 From nobody Fri Sep 19 02:17:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 426A8C4332F for ; Tue, 29 Nov 2022 21:09:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236852AbiK2VJl (ORCPT ); Tue, 29 Nov 2022 16:09:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233743AbiK2VJH (ORCPT ); Tue, 29 Nov 2022 16:09:07 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A631EE32 for ; Tue, 29 Nov 2022 13:09:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756145; x=1701292145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+c+idxLi34QmYjm2JNwF3yjYRC3bi0/GYB7hm+1xYXc=; b=iMSjoF5xPeqZPvkk5bmJPC5ioZnaWGMJrbWs0aE7KSglJw2rXcjz7VWA sFmUlpEvTYDEzYzpEByAftwRjKxEjIwjRVWwF1zrXDHKrEvoDhLvQng5y KwiTAt7JxI19NQpRqhefjZN0j1VJym7xSRDwjQ0GD94Fd45TuwuKIlzng svXp6theL+SkbbBH13Cnf7afNdtzuMwNcnUe2ttvuAzvbT8F+i0Yf15sA nmSashcbh+93ZOq1rICl+VtDh35lF9yU5UcyIH7DjbrcCtO/kmBjrsK+t RUfIRY4AphpGlWT9/GEboYVT+Pd2+ErxPHeMZrjPnQa6bXuMhgEmWua5/ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083139" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083139" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:04 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066211" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066211" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:04 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 4/7] x86/microcode/core: Take a snapshot before and after applying microcode Date: Tue, 29 Nov 2022 13:08:29 -0800 Message-Id: <20221129210832.107850-5-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The kernel caches features about each CPU's features at boot in an x86_capability[] structure. The microcode update takes one snapshot and compares it with the saved copy at boot. However, the capabilities in the boot copy can be turned off as a result of certain command line parameters or configuration restrictions. This can cause a mismatch when comparing the values before and after the microcode update. microcode_check() is called after an update to report any previously cached CPUID bits might have changed due to the update. Ignore the capabilities recorded at boot. Take a new snapshot before the update and compare with a snapshot after the update to eliminate the false warning. Fixes: 1008c52c09dc ("x86/CPU: Add a microcode loader callback") Signed-off-by: Ashok Raj Reviewed-by: Tony Luck --- arch/x86/kernel/cpu/microcode/core.c | 36 ++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index ef24e1d228d0..fab2010ff368 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -431,12 +431,28 @@ static int __reload_late(void *info) return ret; } =20 +static void copy_cpu_caps(struct cpuinfo_x86 *info) +{ + /* Reload CPUID max function as it might've changed. */ + info->cpuid_level =3D cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + memcpy(info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(info->x86_capability)); + + get_cpu_cap(info); +} + /* * The microcode loader calls this upon late microcode load to recheck fea= tures, * only when microcode has been updated. Caller holds microcode_mutex and = CPU * hotplug lock. */ -static void microcode_check(void) +static void microcode_check(struct cpuinfo_x86 *orig) { struct cpuinfo_x86 info; =20 @@ -446,15 +462,13 @@ static void microcode_check(void) info.cpuid_level =3D cpuid_eax(0); =20 /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). - */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x= 86_capability)); + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + copy_cpu_caps(&info); =20 - get_cpu_cap(&info); - - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, + if (!memcmp(&info.x86_capability, &orig->x86_capability, sizeof(info.x86_capability))) return; =20 @@ -469,6 +483,7 @@ static void microcode_check(void) static int microcode_reload_late(void) { int old =3D boot_cpu_data.microcode, ret; + struct cpuinfo_x86 info; =20 pr_err("Attempting late microcode loading - it is dangerous and taints th= e kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -476,9 +491,10 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); =20 + copy_cpu_caps(&info); ret =3D stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret =3D=3D 0) - microcode_check(); + microcode_check(&info); =20 pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); --=20 2.34.1 From nobody Fri Sep 19 02:17:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE43AC433FE for ; Tue, 29 Nov 2022 21:09:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236849AbiK2VJg (ORCPT ); Tue, 29 Nov 2022 16:09:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236427AbiK2VJH (ORCPT ); Tue, 29 Nov 2022 16:09:07 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EE94101F2 for ; Tue, 29 Nov 2022 13:09:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756146; x=1701292146; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aFHPQK+2Oph+JjnPWlBfQ8UflwxbR0mKWG54lIPAftU=; b=Kju5GOzbuX/5maJj+OH88jQB57hEY6ntKq0LAIyDBbn+Ui3z/fd+wvIo 00QKyzaeIrOdmHnRigR7B0nKqLxZo2CZ+6lxuspAABL2+rGvvoFuMa1Nl INTNwc9PIeWmEkI4WKDfKAQX16+ZZew/NSD+BYWujB4gzNXDNyRkkLyyi D+UynJ4oHL4NrSOTnyfGqMOaY63avWzi/zmGuu/EWTPYkTqwA45O5PmOJ p32dSoq6eg29mw5oXt9VsaoB1wvBrsfHUrFpYRCrJv4YnZQ28Xc1cjCAv GbfMxuTF3H5j++EVwazBR41TM20vXIrMm3iVPi9OSd9WJBvBeIxdClQ9L g==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083142" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083142" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066216" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066216" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:04 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 5/7] x86/microcode/intel: Prepare the print_ucode_rev to simply take a rev to print Date: Tue, 29 Nov 2022 13:08:30 -0800 Message-Id: <20221129210832.107850-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of passing a struct ucode_cpu_info, just pass the rev to print. Next patch will permit printing old and new revisions after an early update. A subsequent patch will print a message when early loading fails. struct ucode_cpu_info is always the current version in the CPU. When loading fails this is the old rev, when its successfully applied its the new rev. That makes the code bit ugly to read. Remove the struct ucode_cpu_info parameter from print_ucode() and let the caller to pass in the revision number to print. No functional change. Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++++------------------ 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index d68b084a17e7..0a4f511e39ea 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -309,10 +309,10 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) * Print ucode update info. */ static void -print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) +print_ucode_info(unsigned int new_rev, unsigned int date) { pr_info_once("microcode updated early to revision 0x%x, date =3D %04x-%02= x-%02x\n", - uci->cpu_sig.rev, + new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); @@ -332,7 +332,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(&uci, current_mc_date); + print_ucode_info(uci.cpu_sig.rev. current_mc_date); delay_ucode_info =3D 0; } } @@ -341,33 +341,23 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(struct ucode_cpu_info *uci) +static void print_ucode(int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; =20 - mc =3D uci->mc; - if (!mc) - return; - delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); =20 *delay_ucode_info_p =3D 1; - *current_mc_date_p =3D mc->hdr.date; + *current_mc_date_p =3D date; } #else =20 -static inline void print_ucode(struct ucode_cpu_info *uci) +static inline void print_ucode(int new_rev, int date) { - struct microcode_intel *mc; - - mc =3D uci->mc; - if (!mc) - return; - - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(new_rev, date); } #endif =20 @@ -407,9 +397,9 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(uci); + print_ucode(uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); =20 return 0; } --=20 2.34.1 From nobody Fri Sep 19 02:17:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A40A9C4332F for ; Tue, 29 Nov 2022 21:09:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236930AbiK2VJp (ORCPT ); Tue, 29 Nov 2022 16:09:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236770AbiK2VJH (ORCPT ); Tue, 29 Nov 2022 16:09:07 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A5DD1275C for ; Tue, 29 Nov 2022 13:09:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756146; x=1701292146; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mNhSx3Rnv+AmLrb00ne/8ykmg4QVntYPSdnoX8ENEXo=; b=L1ZVpALiyIZ01wWHD/CvedubZSeHxDnirkWpr80wydZs/IHz3QJJQ59/ bkrezCihOAQokgGMDW5disB/YbnSqu9I1/17T18cE2Ddy5Y5TWECaZJDQ EC2K0kckbnWkWi99Ab9B99g+9Av8RnkcFW7n1oNWh90pjlWbZUhRoTzYu Dnkz85CuGHg1MUY6DawNmrI6xB58tl7UxiM/knpNdsQB+NIWLf4LG4oYU cl5hC70awS6xBTLpuXluy/oCLb92dZ5UNECLB1BcTjabFaoqG29qxmxWj 181IKXuEYvQwvd5I284451TEf23Jm4zMtZLUh769o38g6H5/SnJ67E/Yl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083145" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083145" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066219" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066219" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:05 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 6/7] x86/microcode/intel: Print old and new rev during early boot Date: Tue, 29 Nov 2022 13:08:31 -0800 Message-Id: <20221129210832.107850-7-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. microcode: early update: 0x2b000041 -> 0x2b000070 date =3D 2000-01-01 Store the early BIOS revision and change the print format to match late loading message from microcode/core.c Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 0a4f511e39ea..3dbcf457f45d 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -309,10 +309,10 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) * Print ucode update info. */ static void -print_ucode_info(unsigned int new_rev, unsigned int date) +print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date =3D %04x-%02= x-%02x\n", - new_rev, + pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); @@ -322,6 +322,7 @@ print_ucode_info(unsigned int new_rev, unsigned int dat= e) =20 static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; =20 /* * Print early updated ucode info after printk works. This is delayed info= dump. @@ -332,7 +333,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev. current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info =3D 0; } } @@ -341,30 +342,33 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; =20 delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p =3D (int *)__pa_nodebug(&early_old_rev); =20 *delay_ucode_info_p =3D 1; *current_mc_date_p =3D date; + *early_old_rev_p =3D old_rev; } #else =20 -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif =20 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; =20 mc =3D uci->mc; if (!mc) @@ -390,6 +394,7 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); =20 + old_rev =3D rev; rev =3D intel_get_microcode_revision(); if (rev !=3D mc->hdr.rev) return -1; @@ -397,9 +402,9 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); =20 return 0; } --=20 2.34.1 From nobody Fri Sep 19 02:17:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6679C433FE for ; Tue, 29 Nov 2022 21:09:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236937AbiK2VJv (ORCPT ); Tue, 29 Nov 2022 16:09:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236522AbiK2VJI (ORCPT ); Tue, 29 Nov 2022 16:09:08 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8C413F41 for ; Tue, 29 Nov 2022 13:09:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669756147; x=1701292147; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=20JuXfzhAsVCbgdOdNtTvhg8467Iyas3sTDbl4soGRo=; b=hadAQMldluMt9tJL7ixJlQtcaB2uBl9ahcRVd0d8TnU/p9c091mXXKBU o4D6gOcvQlaYhskVKAimk6vkVRdpTz7g/VGUkPeD5pq5Ggq/S3q8yIaqv AAc7SzNXC2X8a2lkDH2hWTXSGvqliJpUL3egB5P4sV0XwspR2qS5cTczB ATHPMa7x1AxDADzsO1I2PPINqIukgxGsW1kkjAoaqJJhMs24ABp3/yAjS uHhXSawjR4ZHWnMXNsH+Kf0UBsWw+82DO+qutshC6f7PsY2/+aU+Hdqpf a4Y0Ys2CJv3NJ79TbpjdE2vsqcDBh5P+wPBjjfD477cm0wrQnNGh0R6B9 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="317083148" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="317083148" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10546"; a="646066222" X-IronPort-AV: E=Sophos;i="5.96,204,1665471600"; d="scan'208";a="646066222" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2022 13:09:05 -0800 From: Ashok Raj To: Borislav Petkov Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , alison.schofield@intel.com, reinette.chatre@intel.com Subject: [Patch V1 7/7] x86/microcode/intel: Print when early microcode loading fails Date: Tue, 29 Nov 2022 13:08:32 -0800 Message-Id: <20221129210832.107850-8-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129210832.107850-1-ashok.raj@intel.com> References: <20221129210832.107850-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently when early microcode loading fails there is no way for user to know that the update failed. Store the failed status and pass it to print_ucode_info() to let early loading failures to captured in console log. Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 29 ++++++++++++++++----------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 3dbcf457f45d..3b299f437e35 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -309,13 +309,14 @@ static bool load_builtin_intel_microcode(struct cpio_= data *cp) * Print ucode update info. */ static void -print_ucode_info(int old_rev, int new_rev, unsigned int date) +print_ucode_info(bool failed, int old_rev, int new_rev, unsigned int date) { - pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", + pr_info_once("early update: 0x%x -> 0x%x, date =3D %04x-%02x-%02x %s\n", old_rev, new_rev, date & 0xffff, date >> 24, - (date >> 16) & 0xff); + (date >> 16) & 0xff, + failed ? "FAILED" : ""); } =20 #ifdef CONFIG_X86_32 @@ -323,6 +324,7 @@ print_ucode_info(int old_rev, int new_rev, unsigned int= date) static int delay_ucode_info; static int current_mc_date; static int early_old_rev; +static bool early_failed; =20 /* * Print early updated ucode info after printk works. This is delayed info= dump. @@ -333,7 +335,7 @@ void show_ucode_info_early(void) =20 if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); + print_ucode_info(early_failed, early_old_rev, uci.cpu_sig.rev, current_m= c_date); delay_ucode_info =3D 0; } } @@ -342,26 +344,28 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode i= nfo in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int old_rev, int new_rev, int date) +static void print_ucode(bool failed, int old_rev, int new_rev, int date) { - struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; int *early_old_rev_p; + bool *early_failed_p; =20 delay_ucode_info_p =3D (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p =3D (int *)__pa_nodebug(¤t_mc_date); early_old_rev_p =3D (int *)__pa_nodebug(&early_old_rev); + early_failed_p =3D (int *)__pa_nodebug(&early_failed); =20 *delay_ucode_info_p =3D 1; *current_mc_date_p =3D date; *early_old_rev_p =3D old_rev; + *early_failed_p =3D failed; } #else =20 -static inline void print_ucode(int old_rev, int new_rev, int date) +static inline void print_ucode(bool failed, int old_rev, int new_rev, int = date) { - print_ucode_info(old_rev, new_rev, date); + print_ucode_info(failed, old_rev, new_rev, date); } #endif =20 @@ -369,6 +373,7 @@ static int apply_microcode_early(struct ucode_cpu_info = *uci, bool early) { struct microcode_intel *mc; u32 rev, old_rev; + int retval =3D 0; =20 mc =3D uci->mc; if (!mc) @@ -397,16 +402,16 @@ static int apply_microcode_early(struct ucode_cpu_inf= o *uci, bool early) old_rev =3D rev; rev =3D intel_get_microcode_revision(); if (rev !=3D mc->hdr.rev) - return -1; + retval =3D -1; =20 uci->cpu_sig.rev =3D rev; =20 if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode(retval, old_rev, mc->hdr.rev, mc->hdr.date); else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(retval, old_rev, uci->cpu_sig.rev, mc->hdr.date); =20 - return 0; + return retval; } =20 int __init save_microcode_in_initrd_intel(void) --=20 2.34.1