From nobody Fri Sep 19 04:10:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9617C4321E for ; Tue, 29 Nov 2022 14:25:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229993AbiK2OZQ (ORCPT ); Tue, 29 Nov 2022 09:25:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234698AbiK2OZH (ORCPT ); Tue, 29 Nov 2022 09:25:07 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 278D1266F for ; Tue, 29 Nov 2022 06:25:07 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso17530410pjt.0 for ; Tue, 29 Nov 2022 06:25:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GBh16wlKK1pVBXMjv15TuW7j92X6+xaNPp74Ke5cwzg=; b=MCBPj1/g120Iv1kMjeuMVMrddfHIEvaxRkOp/ainQWEfZaR+H8Me+9I6DCNqlm+T0U xJNT5M0QZZ8806GKqxPZeqtWvYNQIFtnHI+bYxXGwoz69DA/ftjhtga+RJhJj0sC0jxw OSbcf/jRQfVJhCA1mW2yPiEPdzSanu2CHsMLpm95kyas7FCvqxsZWDMJEwlecjovJ6wZ IeOIT6ug2PteDDDHCzEuMxVuiy5F/0FCdnTZN12aSxiWELz9hYRwIn7Gt2oNCijWu1U+ 1AOqbsplUFy6XRes+Xvcacp2+J+5vIgLrhWUzaVghN2aRLGD7oVDDWgZVVugZRtsVTYv p7Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GBh16wlKK1pVBXMjv15TuW7j92X6+xaNPp74Ke5cwzg=; b=Ov98LWhV8egoZ3qC7MR3xUa448qU4CM3GlxLpXXZLDumvtCZ3PCK2DpZsKeBtL/wTd DdJIVtPjPeOrRqdkT9sVroadKQJECsLZ4o2gFlsJ9a//ozfegVatXk/PVwYRM4GSchlN I8d63QvpS8IBoehMTlkAoAIIZUzNia19407TRr0ZSDXxG7N2O5GxvQLO1CjUtWcvGbRW J0//PAa2zgNn0bcSdKVmNZjlyxXfOqnq42RE0XxZDQMswg9CGy7dXCu9YiAQJBjWPEh7 NEoemdy3vnt5d8+YCKdjt3q1Scq4oxjZPhl/3Yhy2wPNm9jkaWJRFqOiZqkyeiy1mOTY ZrCQ== X-Gm-Message-State: ANoB5pkiT7/SAvUMJCNiLawXEKfOxHH82I+9a5hHwOhoaHTb18ZGPXKZ P73/YQtnjwCeGxkE35LEh5v4bg== X-Google-Smtp-Source: AA0mqf7Zs4NNRjRlp2Pqboqc1Lm1mhDRLOAyP10co5P7bSMxQUPRIiN0s46dBZLX9R12MDZEweS/uQ== X-Received: by 2002:a17:902:ef4c:b0:189:8b14:55bd with SMTP id e12-20020a170902ef4c00b001898b1455bdmr10500197plx.25.1669731906522; Tue, 29 Nov 2022 06:25:06 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.84.98]) by smtp.gmail.com with ESMTPSA id l12-20020a170903120c00b00176a2d23d1asm11039076plh.56.2022.11.29.06.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 06:25:06 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra Subject: [PATCH v13 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Tue, 29 Nov 2022 19:54:44 +0530 Message-Id: <20221129142449.886518-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221129142449.886518-1-apatel@ventanamicro.com> References: <20221129142449.886518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ =20 #include =20 +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ =20 #include #include +#include +#include #include #include =20 +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node =3D fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 499e5f81b3fe..9066467e99e4 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops= =3D { .xlate =3D irq_domain_xlate_onecell, }; =20 +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -126,6 +131,8 @@ static int __init riscv_intc_init(struct device_node *n= ode, return rc; } =20 + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, --=20 2.34.1