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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id g3-20020adffc83000000b0024207ed4ce0sm7711817wrr.58.2022.11.28.03.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 03:18:01 -0800 (PST) Sender: Tomeu Vizoso From: Tomeu Vizoso Cc: italonicola@collabora.com, Tomeu Vizoso , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/5] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Date: Mon, 28 Nov 2022 12:17:36 +0100 Message-Id: <20221128111740.39003-4-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128111740.39003-1-tomeu.vizoso@collabora.com> References: <20221128111740.39003-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Based on power initialization sequence in downstream driver. Signed-off-by: Tomeu Vizoso Reviewed-by: Neil Armstrong --- drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meso= n-ee-pwrc.c index dd5f2a13ceb5..dfbf0b1c7d29 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -46,6 +46,9 @@ #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) =20 +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) + struct meson_ee_pwrc; struct meson_ee_pwrc_domain; =20 @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = =3D SM1_EE_PD(17); static struct meson_ee_pwrc_top_domain sm1_pwrc_pci =3D SM1_EE_PD(18); static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d =3D SM1_EE_PD(19); =20 +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna =3D { \ + .sleep_reg =3D GX_AO_RTI_GEN_PWR_SLEEP0, \ + .sleep_mask =3D BIT(16) | BIT(17), \ + .iso_reg =3D GX_AO_RTI_GEN_PWR_ISO0, \ + .iso_mask =3D BIT(16) | BIT(17), \ + }; + /* Memory PD Domains */ =20 #define VPU_MEMPD(__reg) \ @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_au= dio[] =3D { { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, }; =20 +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] =3D { + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) }, + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name =3D __name, \ @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domai= ns[] =3D { [PWRC_G12A_VPU_ID] =3D VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, pwrc_ee_is_powered_off, 11, 2), [PWRC_G12A_ETH_ID] =3D MEM_PD("ETH", meson_pwrc_mem_eth), + [PWRC_G12A_NNA_ID] =3D TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, + pwrc_ee_is_powered_off), }; =20 static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] =3D { --=20 2.38.1