From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14496C433FE for ; Mon, 28 Nov 2022 02:08:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229729AbiK1CH6 (ORCPT ); Sun, 27 Nov 2022 21:07:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229504AbiK1CHs (ORCPT ); Sun, 27 Nov 2022 21:07:48 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37EFB10A8; Sun, 27 Nov 2022 18:07:44 -0800 (PST) X-UUID: d3808596b81e40a28cacf68676afcaa9-20221128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; 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Mon, 28 Nov 2022 10:07:38 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 10:07:37 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH 1/9] spi: mtk-snfi: add snfi support for mt7986 IC Date: Mon, 28 Nov 2022 10:06:05 +0800 Message-ID: <20221128020613.14821-2-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> References: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" add snfi support for mt7986 IC Signed-off-by: Xiangsheng Hou --- drivers/spi/spi-mtk-snfi.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index d66bf9762557..fa8412ba20e2 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -126,7 +126,8 @@ #define STR_DATA BIT(0) =20 #define NFI_STA 0x060 -#define NFI_NAND_FSM GENMASK(28, 24) +#define NFI_NAND_FSM_7622 GENMASK(28, 24) +#define NFI_NAND_FSM_7986 GENMASK(29, 23) #define NFI_FSM GENMASK(19, 16) #define READ_EMPTY BIT(12) =20 @@ -158,6 +159,7 @@ #define MAS_WR GENMASK(5, 3) #define MAS_RDDLY GENMASK(2, 0) #define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) +#define NFI_MASTERSTA_MASK_7986 3 =20 // SNFI registers #define SNF_MAC_CTL 0x500 @@ -220,6 +222,11 @@ =20 static const u8 mt7622_spare_sizes[] =3D { 16, 26, 27, 28 }; =20 +static const u8 mt7986_spare_sizes[] =3D { + 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, + 74 +}; + struct mtk_snand_caps { u16 sector_size; u16 max_sectors; @@ -230,6 +237,7 @@ struct mtk_snand_caps { bool bbm_swap; bool empty_page_check; u32 mastersta_mask; + u32 nandfsm_mask; =20 const u8 *spare_sizes; u32 num_spare_size; @@ -244,6 +252,7 @@ static const struct mtk_snand_caps mt7622_snand_caps = =3D { .bbm_swap =3D false, .empty_page_check =3D false, .mastersta_mask =3D NFI_MASTERSTA_MASK_7622, + .nandfsm_mask =3D NFI_NAND_FSM_7622, .spare_sizes =3D mt7622_spare_sizes, .num_spare_size =3D ARRAY_SIZE(mt7622_spare_sizes) }; @@ -257,10 +266,25 @@ static const struct mtk_snand_caps mt7629_snand_caps = =3D { .bbm_swap =3D true, .empty_page_check =3D false, .mastersta_mask =3D NFI_MASTERSTA_MASK_7622, + .nandfsm_mask =3D NFI_NAND_FSM_7622, .spare_sizes =3D mt7622_spare_sizes, .num_spare_size =3D ARRAY_SIZE(mt7622_spare_sizes) }; =20 +static const struct mtk_snand_caps mt7986_snand_caps =3D { + .sector_size =3D 1024, + .max_sectors =3D 8, + .fdm_size =3D 8, + .fdm_ecc_size =3D 1, + .fifo_size =3D 64, + .bbm_swap =3D true, + .empty_page_check =3D true, + .mastersta_mask =3D NFI_MASTERSTA_MASK_7986, + .nandfsm_mask =3D NFI_NAND_FSM_7986, + .spare_sizes =3D mt7986_spare_sizes, + .num_spare_size =3D ARRAY_SIZE(mt7986_spare_sizes) +}; + struct mtk_snand_conf { size_t page_size; size_t oob_size; @@ -360,7 +384,7 @@ static int mtk_nfi_reset(struct mtk_snand *snf) } =20 ret =3D readl_poll_timeout(snf->nfi_base + NFI_STA, val, - !(val & (NFI_FSM | NFI_NAND_FSM)), 0, + !(val & (NFI_FSM | snf->caps->nandfsm_mask)), 0, SNFI_POLL_INTERVAL); if (ret) { dev_err(snf->dev, "Failed to reset NFI\n"); @@ -1295,6 +1319,7 @@ static irqreturn_t mtk_snand_irq(int irq, void *id) static const struct of_device_id mtk_snand_ids[] =3D { { .compatible =3D "mediatek,mt7622-snand", .data =3D &mt7622_snand_caps }, { .compatible =3D "mediatek,mt7629-snand", .data =3D &mt7629_snand_caps }, + { .compatible =3D "mediatek,mt7986-snand", .data =3D &mt7986_snand_caps }, {}, }; =20 --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A834C46467 for ; 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Mon, 28 Nov 2022 10:07:39 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH 2/9] spi: mtk-snfi: change default page format to setup default setting Date: Mon, 28 Nov 2022 10:06:06 +0800 Message-ID: <20221128020613.14821-3-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> References: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Change default page format to setup default setting since the sector size 1024 on mt7986 will lead to probe fail. Signed-off-by: Xiangsheng Hou --- drivers/spi/spi-mtk-snfi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index fa8412ba20e2..719fc6f53ab1 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -1430,8 +1430,7 @@ static int mtk_snand_probe(struct platform_device *pd= ev) =20 // setup an initial page format for ops matching page_cache_op template // before ECC is called. - ret =3D mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, - ms->caps->spare_sizes[0]); + ret =3D mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64); if (ret) { dev_err(ms->dev, "failed to set initial page format\n"); goto disable_clk; --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53DBFC433FE for ; Mon, 28 Nov 2022 02:08:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229708AbiK1CIE (ORCPT ); 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charset="utf-8" add optional nfi_hclk which needed for mt7986 Signed-off-by: Xiangsheng Hou --- drivers/spi/spi-mtk-snfi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 719fc6f53ab1..85644308df23 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -297,6 +297,7 @@ struct mtk_snand { struct device *dev; struct clk *nfi_clk; struct clk *pad_clk; + struct clk *nfi_hclk; void __iomem *nfi_base; int irq; struct completion op_done; @@ -1339,7 +1340,16 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) dev_err(ms->dev, "unable to enable pad clk\n"); goto err1; } + ret =3D clk_prepare_enable(ms->nfi_hclk); + if (ret) { + dev_err(ms->dev, "unable to enable nfi hclk\n"); + goto err2; + } + return 0; + +err2: + clk_disable_unprepare(ms->pad_clk); err1: clk_disable_unprepare(ms->nfi_clk); return ret; @@ -1347,6 +1357,7 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) =20 static void mtk_snand_disable_clk(struct mtk_snand *ms) { + clk_disable_unprepare(ms->nfi_hclk); clk_disable_unprepare(ms->pad_clk); clk_disable_unprepare(ms->nfi_clk); } @@ -1401,6 +1412,13 @@ static int mtk_snand_probe(struct platform_device *p= dev) goto release_ecc; } =20 + ms->nfi_hclk =3D devm_clk_get_optional(&pdev->dev, "nfi_hclk"); + if (IS_ERR(ms->nfi_hclk)) { + ret =3D PTR_ERR(ms->nfi_hclk); + dev_err(&pdev->dev, "unable to get nfi_hclk, err =3D %d\n", ret); + goto release_ecc; + } + ret =3D mtk_snand_enable_clk(ms); if (ret) goto release_ecc; --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA61CC43217 for ; Mon, 28 Nov 2022 02:08:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229821AbiK1CIG (ORCPT ); Sun, 27 Nov 2022 21:08:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229794AbiK1CH6 (ORCPT ); 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charset="utf-8" add ecc support fot mt7986 IC Signed-off-by: Xiangsheng Hou --- drivers/mtd/nand/ecc-mtk.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c index 9f9b201fe706..c2f6cfa76a04 100644 --- a/drivers/mtd/nand/ecc-mtk.c +++ b/drivers/mtd/nand/ecc-mtk.c @@ -79,6 +79,10 @@ static const u8 ecc_strength_mt7622[] =3D { 4, 6, 8, 10, 12 }; =20 +static const u8 ecc_strength_mt7986[] =3D { + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 +}; + enum mtk_ecc_regs { ECC_ENCPAR00, ECC_ENCIRQ_EN, @@ -483,6 +487,17 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = =3D { .pg_irq_sel =3D 0, }; =20 +static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 =3D { + .err_mask =3D 0x1f, + .err_shift =3D 8, + .ecc_strength =3D ecc_strength_mt7986, + .ecc_regs =3D mt2712_ecc_regs, + .num_ecc_strength =3D 11, + .ecc_mode_shift =3D 5, + .parity_bits =3D 14, + .pg_irq_sel =3D 1, +}; + static const struct of_device_id mtk_ecc_dt_match[] =3D { { .compatible =3D "mediatek,mt2701-ecc", @@ -493,6 +508,9 @@ static const struct of_device_id mtk_ecc_dt_match[] =3D= { }, { .compatible =3D "mediatek,mt7622-ecc", .data =3D &mtk_ecc_caps_mt7622, + }, { + .compatible =3D "mediatek,mt7986-ecc", + .data =3D &mtk_ecc_caps_mt7986, }, {}, }; --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18D79C43217 for ; Mon, 28 Nov 2022 02:08:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229833AbiK1CIK (ORCPT ); Sun, 27 Nov 2022 21:08:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbiK1CIB (ORCPT ); Sun, 27 Nov 2022 21:08:01 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34A065FCC; Sun, 27 Nov 2022 18:07:56 -0800 (PST) X-UUID: c69ff013172c47bea53e2ca8ffc97a88-20221128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; 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charset="utf-8" 1. add mt7986 IC bindings 2. add optional nfi_hclk property which needed for mt7986 Signed-off-by: Xiangsheng Hou --- .../devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.ya= ml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index 6e6e02c91780..ee20075cd0e7 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -26,6 +26,7 @@ properties: enum: - mediatek,mt7622-snand - mediatek,mt7629-snand + - mediatek,mt7986-snand =20 reg: items: @@ -36,14 +37,19 @@ properties: - description: NFI interrupt =20 clocks: + minItems: 2 items: - description: clock used for the controller - description: clock used for the SPI bus + - description: clock used for the AHB bus dma bus, this depends on + hardware design, so this is optional. =20 clock-names: + minItems: 2 items: - const: nfi_clk - const: pad_clk + - const: nfi_hclk =20 nand-ecc-engine: description: device-tree node of the accompanying ECC engine. --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74411C43217 for ; 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Mon, 28 Nov 2022 10:07:53 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 10:07:51 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH 6/9] spi: mtk-snfi: add snfi sample delay and read latency adjustment Date: Mon, 28 Nov 2022 10:06:10 +0800 Message-ID: <20221128020613.14821-7-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> References: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add snfi sample delay and read latency adjustment which can get from dts property. Signed-off-by: Xiangsheng Hou --- drivers/spi/spi-mtk-snfi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 85644308df23..e8587cf2aff2 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -195,6 +195,8 @@ #define DATA_READ_MODE_X4 2 #define DATA_READ_MODE_DUAL 5 #define DATA_READ_MODE_QUAD 6 +#define DATA_READ_LATCH_LAT GENMASK(9, 8) +#define DATA_READ_LATCH_LAT_S 8 #define PG_LOAD_CUSTOM_EN BIT(7) #define DATARD_CUSTOM_EN BIT(6) #define CS_DESELECT_CYC_S 0 @@ -205,6 +207,7 @@ =20 #define SNF_DLY_CTL3 0x548 #define SFCK_SAM_DLY_S 0 +#define SFCK_SAM_DLY GENMASK(5, 0) =20 #define SNF_STA_CTL1 0x550 #define CUS_PG_DONE BIT(28) @@ -1368,6 +1371,7 @@ static int mtk_snand_probe(struct platform_device *pd= ev) const struct of_device_id *dev_id; struct spi_controller *ctlr; struct mtk_snand *ms; + u32 val =3D 0; int ret; =20 dev_id =3D of_match_node(mtk_snand_ids, np); @@ -1446,6 +1450,15 @@ static int mtk_snand_probe(struct platform_device *p= dev) // switch to SNFI mode nfi_write32(ms, SNF_CFG, SPI_MODE); =20 + ret =3D of_property_read_u32(np, "rx-sample-delay", &val); + if (!ret) + nfi_rmw32(ms, SNF_DLY_CTL3, SFCK_SAM_DLY, val); + + ret =3D of_property_read_u32(np, "rx-latch-latency", &val); + if (!ret) + nfi_rmw32(ms, SNF_MISC_CTL, DATA_READ_LATCH_LAT, + val << DATA_READ_LATCH_LAT_S); + // setup an initial page format for ops matching page_cache_op template // before ECC is called. ret =3D mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64); --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A1D6C352A1 for ; Mon, 28 Nov 2022 02:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229848AbiK1CI3 (ORCPT ); Sun, 27 Nov 2022 21:08:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229775AbiK1CIL (ORCPT ); Sun, 27 Nov 2022 21:08:11 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F64963DB; Sun, 27 Nov 2022 18:08:03 -0800 (PST) X-UUID: 1c6084a1216243fc9068014507a06a8e-20221128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=e8ryU+C/Jl2eGzU8a8lflF+NAwn4pUDJzVpIHRS2n7Y=; b=R3868j13wckwSCtYoFuUWEHItyz4JcIaHAOLRiXqmNO3C4rE3Adj4Y8KeJpyMIFoohAefGy3vudX8gHIb9qkKofd6lgIK5vInPTHGurFWL6v7ITXxBgNSj1qwluKPYe7dZBVG+G36yWBSPYTr9MrY/yUMm/C3iR5YTQ5/ywW7mE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:20f0cf1b-0c92-44ea-b62d-95d298558539,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:dcaaed0,CLOUDID:0aa0721e-5e1d-4ab5-ab8e-3e04efc02b30,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 1c6084a1216243fc9068014507a06a8e-20221128 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1438185669; Mon, 28 Nov 2022 10:07:57 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 28 Nov 2022 10:07:56 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 10:07:54 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH 7/9] dt-bindings: spi: mtk-snfi: add two timing delay property Date: Mon, 28 Nov 2022 10:06:11 +0800 Message-ID: <20221128020613.14821-8-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> References: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" add rx-sample-delay and rx-latch-latency property. Signed-off-by: Xiangsheng Hou --- .../bindings/spi/mediatek,spi-mtk-snfi.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.ya= ml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index ee20075cd0e7..367862688e92 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -55,6 +55,22 @@ properties: description: device-tree node of the accompanying ECC engine. $ref: /schemas/types.yaml#/definitions/phandle =20 + rx-sample-delay: + description: Rx delay to sample data with this value, the valid + values are from 0 to 47. The delay is smaller than + the rx-latch-latency. + $ref: /schemas/types.yaml#/definitions/uint32 + minItems: 0 + maxItems: 47 + default: 0 + + rx-latch-latency: + description: Rx delay to sample data with this value, the value + unit is clock cycle. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + required: - compatible - reg --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22A3DC352A1 for ; Mon, 28 Nov 2022 02:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229926AbiK1CId (ORCPT ); Sun, 27 Nov 2022 21:08:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbiK1CIN (ORCPT ); Sun, 27 Nov 2022 21:08:13 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3122C5FC6; Sun, 27 Nov 2022 18:08:06 -0800 (PST) X-UUID: d6641431d4cf4f8ba3872537d7c01ce2-20221128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=x2ZO9T8uDBfvg9Y7/Aj3WgqyBAmho6hFPvG3GNVeqUM=; b=APR/Bb2WvRqMpWbMEu36Aflgqv67msoHCjNx/toaDlTt7qi5BOGUEprV94y1iB5xFr22oQOvuvaQfrCqS3Z4gPnIkqeS/yw+w6zD5UnA4icWGnviq9s9grFU7TM5n3oT3W3aWfFM9X/FsDoNmc9vlBuhjkOvlCFRQI3l6bTYWw4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:cf11ef01-7144-4009-899e-684c8ba1a9e3,IP:0,U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:57a0721e-5e1d-4ab5-ab8e-3e04efc02b30,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: d6641431d4cf4f8ba3872537d7c01ce2-20221128 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 895200316; Mon, 28 Nov 2022 10:08:00 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 28 Nov 2022 10:07:58 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 10:07:57 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH 8/9] dt-bindings: mtd: Split ECC engine with rawnand controller Date: Mon, 28 Nov 2022 10:06:12 +0800 Message-ID: <20221128020613.14821-9-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> References: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Split MediaTek ECC engine with rawnand controller and convert to YAML schema. Signed-off-by: Xiangsheng Hou --- .../bindings/mtd/mtk,nand-ecc-engine.yaml | 60 ++++++ .../devicetree/bindings/mtd/mtk-nand.txt | 176 ------------------ .../devicetree/bindings/mtd/mtk-nand.yaml | 92 +++++++++ 3 files changed, 152 insertions(+), 176 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engi= ne.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.yaml diff --git a/Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml= b/Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml new file mode 100644 index 000000000000..80321157e928 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mtk,nand-ecc-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs NAND ECC engine + +maintainers: + - Xiangsheng Hou + +description: | + MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. + +properties: + compatible: + enum: + - mediatek,mt2701-ecc + - mediatek,mt2712-ecc + - mediatek,mt7622-ecc + + reg: + items: + - description: Base physical address and size of ECC. + + interrupts: + items: + - description: ECC interrupt + + clocks: + minItems: 1 + items: + - description: clock used for the controller + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + bch: ecc@1100e000 { + compatible =3D "mediatek,mt2701-ecc"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI_ECC>; + }; + }; + diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documenta= tion/devicetree/bindings/mtd/mtk-nand.txt deleted file mode 100644 index 4d3ec5e4ff8a..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt +++ /dev/null @@ -1,176 +0,0 @@ -MTK SoCs NAND FLASH controller (NFC) DT binding - -This file documents the device tree bindings for MTK SoCs NAND controllers. -The functional split of the controller requires two drivers to operate: -the nand controller interface driver and the ECC engine driver. - -The hardware description for both devices must be captured as device -tree nodes. - -1) NFC NAND Controller Interface (NFI): -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The first part of NFC is NAND Controller Interface (NFI) HW. -Required NFI properties: -- compatible: Should be one of - "mediatek,mt2701-nfc", - "mediatek,mt2712-nfc", - "mediatek,mt7622-nfc". -- reg: Base physical address and size of NFI. -- interrupts: Interrupts of NFI. -- clocks: NFI required clocks. -- clock-names: NFI clocks internal name. -- ecc-engine: Required ECC Engine node. -- #address-cells: NAND chip index, should be 1. -- #size-cells: Should be 0. - -Example: - - nandc: nfi@1100d000 { - compatible =3D "mediatek,mt2701-nfc"; - reg =3D <0 0x1100d000 0 0x1000>; - interrupts =3D ; - clocks =3D <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names =3D "nfi_clk", "pad_clk"; - ecc-engine =3D <&bch>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - -Platform related properties, should be set in {platform_name}.dts: -- children nodes: NAND chips. - -Children nodes properties: -- reg: Chip Select Signal, default 0. - Set as reg =3D <0>, <1> when need 2 CS. -Optional: -- nand-on-flash-bbt: Store BBT on NAND Flash. -- nand-ecc-mode: the NAND ecc mode (check driver for supported modes) -- nand-ecc-step-size: Number of data bytes covered by a single ECC step. - valid values: - 512 and 1024 on mt2701 and mt2712. - 512 only on mt7622. - 1024 is recommended for large page NANDs. -- nand-ecc-strength: Number of bits to correct per ECC step. - The valid values that each controller supports: - mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60. - mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80. - mt7622: 4, 6, 8, 10, 12, 14, 16. - The strength should be calculated as follows: - E =3D (S - F) * 8 / B - S =3D O / (P / Q) - E : nand-ecc-strength. - S : spare size per sector. - F : FDM size, should be in the range [1,8]. - It is used to store free oob data. - O : oob size. - P : page size. - Q : nand-ecc-step-size. - B : number of parity bits needed to correct - 1 bitflip. - According to MTK NAND controller design, - this number depends on max ecc step size - that MTK NAND controller supports. - If max ecc step size supported is 1024, - then it should be always 14. And if max - ecc step size is 512, then it should be - always 13. - If the result does not match any one of the listed - choices above, please select the smaller valid value from - the list. - (otherwise the driver will do the adjustment at runtime) -- pinctrl-names: Default NAND pin GPIO setting name. -- pinctrl-0: GPIO setting node. - -Example: - &pio { - nand_pins_default: nanddefault { - pins_dat { - pinmux =3D , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength =3D ; - bias-pull-up; - }; - - pins_we { - pinmux =3D ; - drive-strength =3D ; - bias-pull-up =3D ; - }; - - pins_ale { - pinmux =3D ; - drive-strength =3D ; - bias-pull-down =3D ; - }; - }; - }; - - &nandc { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&nand_pins_default>; - nand@0 { - reg =3D <0>; - nand-on-flash-bbt; - nand-ecc-mode =3D "hw"; - nand-ecc-strength =3D <24>; - nand-ecc-step-size =3D <1024>; - }; - }; - -NAND chip optional subnodes: -- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt - -Example: - nand@0 { - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - preloader@0 { - label =3D "pl"; - read-only; - reg =3D <0x00000000 0x00400000>; - }; - android@00400000 { - label =3D "android"; - reg =3D <0x00400000 0x12c00000>; - }; - }; - }; - -2) ECC Engine: -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -Required BCH properties: -- compatible: Should be one of - "mediatek,mt2701-ecc", - "mediatek,mt2712-ecc", - "mediatek,mt7622-ecc". -- reg: Base physical address and size of ECC. -- interrupts: Interrupts of ECC. -- clocks: ECC required clocks. -- clock-names: ECC clocks internal name. - -Example: - - bch: ecc@1100e000 { - compatible =3D "mediatek,mt2701-ecc"; - reg =3D <0 0x1100e000 0 0x1000>; - interrupts =3D ; - clocks =3D <&pericfg CLK_PERI_NFI_ECC>; - clock-names =3D "nfiecc_clk"; - }; diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.yaml b/Document= ation/devicetree/bindings/mtd/mtk-nand.yaml new file mode 100644 index 000000000000..47a1334bcddd --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mtk-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC) device tree bind= ings + +maintainers: + - Xiangsheng Hou + +allOf: + - $ref: "nand-controller.yaml#" + +properties: + compatible: + enum: + - mediatek,mt2701-nfc + - mediatek,mt2712-nfc + - mediatek,mt7622-nfc + + reg: + items: + - description: Base physical address and size of NFI. + + interrupts: + items: + - description: NFI interrupt + + clocks: + minItems: 2 + items: + - description: clock used for the controller + - description: clock used for the pad + + clock-names: + minItems: 2 + items: + - const: nfi_clk + - const: pad_clk + + nand-ecc-engine: + description: Required ECC Engine node + $ref: /schemas/types.yaml#/definitions/phandle + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - nand-ecc-engine + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + nandc: nfi@1100d000 { + compatible =3D "mediatek,mt2701-nfc"; + reg =3D <0 0x1100d000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names =3D "nfi_clk", "pad_clk"; + nand-ecc-engine =3D <&bch>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + bch: ecc@1100e000 { + compatible =3D "mediatek,mt2701-ecc"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI_ECC>; + }; + }; --=20 2.25.1 From nobody Sat Sep 21 09:36:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44C15C433FE for ; Mon, 28 Nov 2022 02:08:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229878AbiK1CIh (ORCPT ); Sun, 27 Nov 2022 21:08:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiK1CIY (ORCPT ); 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Mon, 28 Nov 2022 10:08:04 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 28 Nov 2022 10:08:03 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 10:08:02 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH 9/9] dt-bindings: mtd: ecc-mtk: add mt7986 IC ecc bindings Date: Mon, 28 Nov 2022 10:06:13 +0800 Message-ID: <20221128020613.14821-10-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> References: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" add mt7986 IC ecc bindings Signed-off-by: Xiangsheng Hou --- Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml= b/Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml index 80321157e928..e5d8e1839fff 100644 --- a/Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml +++ b/Documentation/devicetree/bindings/mtd/mtk,nand-ecc-engine.yaml @@ -18,6 +18,7 @@ properties: - mediatek,mt2701-ecc - mediatek,mt2712-ecc - mediatek,mt7622-ecc + - mediatek,mt7986-ecc =20 reg: items: --=20 2.25.1