From nobody Sat Feb 7 17:49:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A05CC4332F for ; Fri, 25 Nov 2022 12:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229602AbiKYM73 (ORCPT ); Fri, 25 Nov 2022 07:59:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229576AbiKYM7G (ORCPT ); Fri, 25 Nov 2022 07:59:06 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7AD04E402; Fri, 25 Nov 2022 04:58:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669381137; x=1700917137; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rDEZLqmqx1Il4mtQD+1kAxu0Wn7dw3dDQlDtYrg5pd8=; b=Y4Ss+10Q+yp/wN/2AZtxUR3vw8xNdaClikv43xfbHTc701S1+XnV2jzI a96vddc+X1rf0iAHIG92GI94GajWwze3cHtf6+Jz4C86KIEVy8wWKR197 2zvdhlpwqycrC2SUihoRwxstvDhmliRNYrLsb01iOK5wufSlVlDIl7jGA 6YBX9YWQyXpEn97jhDVh6JTJ33LbVfLwER5873+foLoOUhpDLLBI100Zf 69nYAxwxK7P7SHdDm/jY6+8P3eB3zS/dIHZNUbpQBxpjvgSjHlWSztmL7 mWfj2v+YDJkayK6A5R3gbuvPVs/hsV4bPdlDII3bqU6oslpc40QqlP3Ou w==; X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="341381289" X-IronPort-AV: E=Sophos;i="5.96,193,1665471600"; d="scan'208";a="341381289" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2022 04:58:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="706061267" X-IronPort-AV: E=Sophos;i="5.96,193,1665471600"; d="scan'208";a="706061267" Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by fmsmga008.fm.intel.com with ESMTP; 25 Nov 2022 04:58:52 -0800 From: Jiaxi Chen To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, ndesaulniers@google.com, alexandre.belloni@bootlin.com, peterz@infradead.org, jpoimboe@kernel.org, chang.seok.bae@intel.com, pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com, jmattson@google.com, sandipan.das@amd.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, fenghua.yu@intel.com, keescook@chromium.org, nathan@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/8] x86: KVM: Advertise AMX-FP16 CPUID to user space Date: Fri, 25 Nov 2022 20:58:41 +0800 Message-Id: <20221125125845.1182922-5-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125125845.1182922-1-jiaxi.chen@linux.intel.com> References: <20221125125845.1182922-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "Chang S. Bae" Latest Intel platform Granite Rapids has introduced a new instruction - AMX-FP16, which performs dot-products of two FP16 tiles and accumulates the results into a packed single precision tile. AMX-FP16 adds FP16 capability and also allows a FP16 GPU trained model to run faster without loss of accuracy or added SW overhead. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[bit 21] AMX-FP16 is on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Given that, define this feature bit like X86_FEATURE_ in kernel. Considering AMX-FP16 itself has no truly kernel usages and /proc/cpuinfo has too much unreadable flags, hide this one in /proc/cpuinfo. Advertise AMX-FP16 to KVM userspace. This is safe because there are no new VMX controls or additional host enabling required for guests to use this feature. Signed-off-by: Chang S. Bae Signed-off-by: Jiaxi Chen Acked-by: Borislav Petkov --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 5cdd57133d90..20059dc33d24 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -309,6 +309,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instruc= tions */ +#define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index f8bf4fb30b96..0e04d1138bca 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -663,7 +663,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); =20 kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) + F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) ); =20 kvm_cpu_cap_mask(CPUID_D_1_EAX, --=20 2.27.0