From nobody Fri Sep 19 11:04:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D633C4332F for ; Fri, 25 Nov 2022 11:22:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229943AbiKYLWT (ORCPT ); Fri, 25 Nov 2022 06:22:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229974AbiKYLVp (ORCPT ); Fri, 25 Nov 2022 06:21:45 -0500 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8B86286D1 for ; Fri, 25 Nov 2022 03:21:44 -0800 (PST) Received: by mail-pg1-x536.google.com with SMTP id q71so3704669pgq.8 for ; Fri, 25 Nov 2022 03:21:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G1ogE3iUjoMSXzLx1NgTul4M3E0f5R6SeuN3d1g+xHg=; b=dnGJBUNJQl0wlLkoDF9rV+Fk3ir0Zo+py6y4hjjjRZOAZtMja3aUacpgOypb2+kVaV vWx9m4ZldeFz7buRLSRXiO6zWXZHVO7qb/W3+16VJYNsrHugMitE3+gm2kfEYXOgPHbU ha8hl0o+yScSTJMIzLFEiSyQxYkm3nGkb0XxrAFOMnKQCoiliUYCmd55WEB1JOQncxyD zbKbRaXkmOgPTlan7WsKeVocPRH3frnEaCQour6xMZkDnmUo2qtI/c540HD6YkmKIrcI 5TsL8g+hAUgRELJp7kqSgLCFEobVRwZEM4QCbadzTFtfcA775XB3Ov3JZlFI9W2NtpXi 6Wlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G1ogE3iUjoMSXzLx1NgTul4M3E0f5R6SeuN3d1g+xHg=; b=mcrYDA4XRdFrzJ4jLcw8JhW5WoQkQ6S/jT/PBKwR8LX3ERF8TxqUp2841aSXY4awQz HLwTRLW/ycigHd6umTl8Z5euH0tArbhweCO6Yq6/9sEB2IatEBhF9LjecBLXqAzE1jrA 7WGJ4D84gSljsZ/RPuh7GvP0sICmPWuKeF/AYVitsmQ9A4N922qEKYgt4rQE2nM1V7Wl 3xu8wub3IQiaqjFVQ4tDmq3lLYDT7bb/Ntck5++mBqzwHhauOlvQnwD1MNV9CZWTeErp SFAdNRkMINs611eLGgyKwwK4ZZn1ZQhfjq6vQ//qL+dconIwchQmEDNoZl2AxF+D9FKc MyFQ== X-Gm-Message-State: ANoB5pnD8FkgLtS9iab/Xhqe5SSYPzLVvSsSs7UFxT+18KqAVavYVcc7 /uSO0eOstWgdqas+Xaey5BoAqw== X-Google-Smtp-Source: AA0mqf50JFV3DpRNLPvltimF6u0clZODoD326IHS8ZXlmnfKizp7cVe3f93LKwRBF7JH++67Ge7yEQ== X-Received: by 2002:a63:dc45:0:b0:44e:46f9:7eeb with SMTP id f5-20020a63dc45000000b0044e46f97eebmr16133001pgj.3.1669375304115; Fri, 25 Nov 2022 03:21:44 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id e66-20020a621e45000000b0057488230704sm2834335pfe.219.2022.11.25.03.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:21:43 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Date: Fri, 25 Nov 2022 16:51:05 +0530 Message-Id: <20221125112105.427045-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221125112105.427045-1-apatel@ventanamicro.com> References: <20221125112105.427045-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when riscv,timer-cant-wake-up DT property is present in the RISC-V timer DT node. This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device based on RISC-V platform capabilities rather than having it set for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Suggested-by: Samuel Holland --- drivers/clocksource/timer-riscv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index a0d66fabf073..0c8bdd168a45 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -28,6 +28,7 @@ #include =20 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); +static bool riscv_timer_cant_wake_cpu; =20 static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) =20 ce->cpumask =3D cpumask_of(cpu); ce->irq =3D riscv_clock_event_irq; + if (riscv_timer_cant_wake_cpu) + ce->features |=3D CLOCK_EVT_FEAT_C3STOP; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); =20 enable_percpu_irq(riscv_clock_event_irq, @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_no= de *n) if (cpuid !=3D smp_processor_id()) return 0; =20 + child =3D of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cant_wake_cpu =3D of_property_read_bool(child, + "riscv,timer-cant-wake-cpu"); + of_node_put(child); + } + domain =3D NULL; child =3D of_get_compatible_child(n, "riscv,cpu-intc"); if (!child) { --=20 2.34.1