From nobody Fri Sep 19 09:24:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61426C4167B for ; Fri, 25 Nov 2022 11:22:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229813AbiKYLVk (ORCPT ); Fri, 25 Nov 2022 06:21:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229649AbiKYLVg (ORCPT ); Fri, 25 Nov 2022 06:21:36 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0F4027918 for ; Fri, 25 Nov 2022 03:21:34 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id g10so3712903plo.11 for ; Fri, 25 Nov 2022 03:21:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bu6gMWlGL1798v9tVBYC6q+OA3VeKQCQFwAOJPQbKO0=; b=To90HQsu+nRhrpBaf8hoVduWXUfZ1tr9GO8p1fFwpVasAb3QZFs9HML/Qrn1vrBE7C 3vsuD281OG3+H1XN4yvrHCeF683B/dTB9o68D0P0JqmhXXS2OFvmXp/ayHdWWhlLbFA1 1CD37gIN/DfDUk5meIAc+lAmcFJmB+nbYa+m+YwDLmYAr9PqnpiIWCEXBAe3MZzVSM4H 6tAdLsJNKS8hamjUTFwrq+Td+h8NOuRo1Z9pgDp60Do59P+x/KYvKWLXjQWiYLdYLzcP rtHK1GwJdups2WWAH6HJ4p+1l+tYOGlUGE0dwQI1jI5Y+xS1T3BdF1HEvknSqfc7YIHL QyGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bu6gMWlGL1798v9tVBYC6q+OA3VeKQCQFwAOJPQbKO0=; b=IBtt8Q9DQ/SpPIIF3jAydi0rZRx8D1tRRWwRpC1X6+IERIh56ijvfQ1l4s9sDw0zJh Ot70CUhi80ffv517Bk0vGlfv+Ibxocik0319Myre0Unw/h6V5JMbnEtBLpmfS3cjcoyr 1ivKyngY+hBonqreWZdl0ixwfV1P1uP1ia6FXtUXhTjqAJG76g5y3CIQ+y/Ss/fo5WU/ HfW1KwncTV7PzN7uOskqoMRvh/gppqKpSOf02MTdjhHPct0o3vBO3cbLrRwcMybxtql8 5DKJcWog7IjFRnDqassgqHhLmS/MgibHK5EMyV8/kcXTIVFjGBbFW3OzC377h2P3sVqz EbnQ== X-Gm-Message-State: ANoB5pnmwk2YDxYpRYDpDyX1pgO+VmjSlYOaj2TiqPKI0DT6aMzmExFG wmAtc+pqfg7eifCOLD23Nj8qGg== X-Google-Smtp-Source: AA0mqf6g24tHjlg8F5EfnWXfFlEVrgU699VXSpbDgg0ghtBXNTb315U16mtrNFdCP2BZ6q5QaQdR2w== X-Received: by 2002:a17:90b:1d45:b0:218:6db5:fd98 with SMTP id ok5-20020a17090b1d4500b002186db5fd98mr41313988pjb.164.1669375293993; Fri, 25 Nov 2022 03:21:33 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id e66-20020a621e45000000b0057488230704sm2834335pfe.219.2022.11.25.03.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:21:33 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , Palmer Dabbelt , Anup Patel Subject: [PATCH v3 1/3] Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend" Date: Fri, 25 Nov 2022 16:51:03 +0530 Message-Id: <20221125112105.427045-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221125112105.427045-1-apatel@ventanamicro.com> References: <20221125112105.427045-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley This reverts commit 232ccac1bd9b5bfe73895f527c08623e7fa0752d. On the subject of suspend, the RISC-V SBI spec states: > Request the SBI implementation to put the calling hart in a platform > specific suspend (or low power) state specified by the suspend_type > parameter. The hart will automatically come out of suspended state and > resume normal execution when it receives an interrupt or platform > specific hardware event. This does not cover whether any given events actually reach the hart or not, just what the hart will do if it receives an event. On PolarFire SoC, and potentially other SiFive based implementations, events from the RISC-V timer do reach a hart during suspend. This is not the case for the implementation on the Allwinner D1 - there timer events are not received during suspend. To fix this, the C3STOP feature was enabled for the timer driver - but this has broken both RCU stall detection and timers generally on PolarFire SoC (and potentially other SiFive based implementations). If an AXI read to the PCIe controller on PolarFire SoC times out, the system will stall, however, with this patch applied, the system just locks up without RCU stalling: io scheduler mq-deadline registered io scheduler kyber registered microchip-pcie 2000000000.pcie: host bridge /soc/pcie@2000000000 ranges: microchip-pcie 2000000000.pcie: MEM 0x2008000000..0x2087ffffff -> 0x0= 008000000 microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer microchip-pcie 2000000000.pcie: axi read request error microchip-pcie 2000000000.pcie: axi read timeout microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer Freeing initrd memory: 7332K Similarly issues were reported with clock_nanosleep() - with a test app that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=3D250 & the blamed commit in place, the sleep times are rounded up to the next jiffy: =3D=3D CPU: 1 =3D=3D =3D=3D CPU: 2 =3D=3D =3D=3D CPU: 3 =3D=3D = =3D=3D CPU: 4 =3D=3D Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179 Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193 Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000 Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000 Samples: 521 Samples: 521 Samples: 521 Samples: 521 Fortunately, the D1 has a second timer, which is "currently used in preference to the RISC-V/SBI timer driver" so a revert here does not hurt operation of D1 in its current form. Ultimately, a DeviceTree property (or node) will be added to encode the behaviour of the timers, but until then revert the addition of CLOCK_EVT_FEAT_C3STOP. Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/ Link: https://github.com/riscv-non-isa/riscv-sbi-doc/issues/98/ Link: https://lore.kernel.org/linux-riscv/bf6d3b1f-f703-4a25-833e-972a44a04= 114@sholland.org/ Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during = CPU suspend") CC: Samuel Holland CC: Anup Patel CC: Palmer Dabbelt Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Acked-by: Samuel Holland Signed-off-by: Conor Dooley Signed-off-by: Anup Patel --- drivers/clocksource/timer-riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 969a552da8d2..a0d66fabf073 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -51,7 +51,7 @@ static int riscv_clock_next_event(unsigned long delta, static unsigned int riscv_clock_event_irq; static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) =3D { .name =3D "riscv_timer_clockevent", - .features =3D CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP, + .features =3D CLOCK_EVT_FEAT_ONESHOT, .rating =3D 100, .set_next_event =3D riscv_clock_next_event, }; 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charset="utf-8" We add DT bindings for a separate RISC-V timer DT node which can be used to describe implementation specific behaviour (such as timer interrupt not triggered during non-retentive suspend). Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Doc= umentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 000000000000..cf53dfff90bc --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mo= de + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cant-wake-cpu: + type: boolean + description: + If present, the timer interrupt can't wake up the CPU from + suspend/idle state. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible =3D "riscv,timer"; + interrupts-extended =3D <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +... --=20 2.34.1 From nobody Fri Sep 19 09:24:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D633C4332F for ; Fri, 25 Nov 2022 11:22:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229943AbiKYLWT (ORCPT ); Fri, 25 Nov 2022 06:22:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229974AbiKYLVp (ORCPT ); Fri, 25 Nov 2022 06:21:45 -0500 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8B86286D1 for ; Fri, 25 Nov 2022 03:21:44 -0800 (PST) Received: by mail-pg1-x536.google.com with SMTP id q71so3704669pgq.8 for ; Fri, 25 Nov 2022 03:21:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G1ogE3iUjoMSXzLx1NgTul4M3E0f5R6SeuN3d1g+xHg=; b=dnGJBUNJQl0wlLkoDF9rV+Fk3ir0Zo+py6y4hjjjRZOAZtMja3aUacpgOypb2+kVaV vWx9m4ZldeFz7buRLSRXiO6zWXZHVO7qb/W3+16VJYNsrHugMitE3+gm2kfEYXOgPHbU ha8hl0o+yScSTJMIzLFEiSyQxYkm3nGkb0XxrAFOMnKQCoiliUYCmd55WEB1JOQncxyD zbKbRaXkmOgPTlan7WsKeVocPRH3frnEaCQour6xMZkDnmUo2qtI/c540HD6YkmKIrcI 5TsL8g+hAUgRELJp7kqSgLCFEobVRwZEM4QCbadzTFtfcA775XB3Ov3JZlFI9W2NtpXi 6Wlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G1ogE3iUjoMSXzLx1NgTul4M3E0f5R6SeuN3d1g+xHg=; b=mcrYDA4XRdFrzJ4jLcw8JhW5WoQkQ6S/jT/PBKwR8LX3ERF8TxqUp2841aSXY4awQz HLwTRLW/ycigHd6umTl8Z5euH0tArbhweCO6Yq6/9sEB2IatEBhF9LjecBLXqAzE1jrA 7WGJ4D84gSljsZ/RPuh7GvP0sICmPWuKeF/AYVitsmQ9A4N922qEKYgt4rQE2nM1V7Wl 3xu8wub3IQiaqjFVQ4tDmq3lLYDT7bb/Ntck5++mBqzwHhauOlvQnwD1MNV9CZWTeErp SFAdNRkMINs611eLGgyKwwK4ZZn1ZQhfjq6vQ//qL+dconIwchQmEDNoZl2AxF+D9FKc MyFQ== X-Gm-Message-State: ANoB5pnD8FkgLtS9iab/Xhqe5SSYPzLVvSsSs7UFxT+18KqAVavYVcc7 /uSO0eOstWgdqas+Xaey5BoAqw== X-Google-Smtp-Source: AA0mqf50JFV3DpRNLPvltimF6u0clZODoD326IHS8ZXlmnfKizp7cVe3f93LKwRBF7JH++67Ge7yEQ== X-Received: by 2002:a63:dc45:0:b0:44e:46f9:7eeb with SMTP id f5-20020a63dc45000000b0044e46f97eebmr16133001pgj.3.1669375304115; Fri, 25 Nov 2022 03:21:44 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id e66-20020a621e45000000b0057488230704sm2834335pfe.219.2022.11.25.03.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:21:43 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Date: Fri, 25 Nov 2022 16:51:05 +0530 Message-Id: <20221125112105.427045-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221125112105.427045-1-apatel@ventanamicro.com> References: <20221125112105.427045-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when riscv,timer-cant-wake-up DT property is present in the RISC-V timer DT node. This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device based on RISC-V platform capabilities rather than having it set for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Suggested-by: Samuel Holland --- drivers/clocksource/timer-riscv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index a0d66fabf073..0c8bdd168a45 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -28,6 +28,7 @@ #include =20 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); +static bool riscv_timer_cant_wake_cpu; =20 static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) =20 ce->cpumask =3D cpumask_of(cpu); ce->irq =3D riscv_clock_event_irq; + if (riscv_timer_cant_wake_cpu) + ce->features |=3D CLOCK_EVT_FEAT_C3STOP; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); =20 enable_percpu_irq(riscv_clock_event_irq, @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_no= de *n) if (cpuid !=3D smp_processor_id()) return 0; =20 + child =3D of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cant_wake_cpu =3D of_property_read_bool(child, + "riscv,timer-cant-wake-cpu"); + of_node_put(child); + } + domain =3D NULL; child =3D of_get_compatible_child(n, "riscv,cpu-intc"); if (!child) { --=20 2.34.1