From nobody Fri Sep 19 09:24:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEA8FC4332F for ; Fri, 25 Nov 2022 11:00:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbiKYLA4 (ORCPT ); Fri, 25 Nov 2022 06:00:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230335AbiKYLAy (ORCPT ); Fri, 25 Nov 2022 06:00:54 -0500 X-Greylist: delayed 398 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 25 Nov 2022 03:00:53 PST Received: from mail-m11880.qiye.163.com (mail-m11880.qiye.163.com [115.236.118.80]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 435814A5AE for ; Fri, 25 Nov 2022 03:00:53 -0800 (PST) Received: from localhost.localdomain (unknown [103.29.142.67]) by mail-m11880.qiye.163.com (Hmail) with ESMTPA id DB18820463; Fri, 25 Nov 2022 18:54:07 +0800 (CST) From: Qiqi Zhang To: dianders@chromium.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, daniel@ffwll.ch Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Qiqi Zhang Subject: [PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug Date: Fri, 25 Nov 2022 18:45:58 +0800 Message-Id: <20221125104558.84616-1-eddy.zhang@rock-chips.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCGEgfVh8fSk9NSxgfHR5CS1UTARMWGhIXJBQOD1 lXWRgSC1lBWUpLSFVJQlVKT0lVTUxZV1kWGg8SFR0UWUFZT0tIVUpKS0hKQ1VKS0tVS1kG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6ND46Pxw4Ej0uFho0GhYKPAEq HBoKCUJVSlVKTU1CSExITU9CS0NMVTMWGhIXVR4fHwJVARMaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlKS0hVSUJVSk9JVU1MWVdZCAFZQUlNSk83Bg++ X-HM-Tid: 0a84ae6c5ef12eb6kusndb18820463 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to the description in ti-sn65dsi86's datasheet: CHA_HSYNC_POLARITY: 0 =3D Active High Pulse. Synchronization signal is high for the sync pulse width. (default) 1 =3D Active Low Pulse. Synchronization signal is low for the sync pulse width. CHA_VSYNC_POLARITY: 0 =3D Active High Pulse. Synchronization signal is high for the sync pulse width. (Default) 1 =3D Active Low Pulse. Synchronization signal is low for the sync pulse width. We should only set these bits when the polarity is negative. Signed-off-by: Qiqi Zhang Reviewed-by: Douglas Anderson Reviewed-by: Tomi Valkeinen Tested-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge= /ti-sn65dsi86.c index 3c3561942eb6..eb24322df721 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -931,9 +931,9 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn= 65dsi86 *pdata) &pdata->bridge.encoder->crtc->state->adjusted_mode; u8 hsync_polarity =3D 0, vsync_polarity =3D 0; =20 - if (mode->flags & DRM_MODE_FLAG_PHSYNC) + if (mode->flags & DRM_MODE_FLAG_NHSYNC) hsync_polarity =3D CHA_HSYNC_POLARITY; - if (mode->flags & DRM_MODE_FLAG_PVSYNC) + if (mode->flags & DRM_MODE_FLAG_NVSYNC) vsync_polarity =3D CHA_VSYNC_POLARITY; =20 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, --=20 2.25.1