From nobody Fri Sep 19 12:45:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21420C4321E for ; Fri, 25 Nov 2022 09:49:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230017AbiKYJtI (ORCPT ); Fri, 25 Nov 2022 04:49:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbiKYJrw (ORCPT ); Fri, 25 Nov 2022 04:47:52 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08BB33D923; Fri, 25 Nov 2022 01:46:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669369581; x=1700905581; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TYXorT9DOo+3WztLtIfe+bDwuNKkxCZCmA5YzIPCu4o=; b=cNJTzwDp8HZPonTt62n1BzPsJvJijb26JqdExB1VqoiwmUII1gF3tv2D PeLm+yleOrTenoH1KtGbWzNzzOHBy9CU93ELXST2g1ZGkZtxPmrjdku7E TvBTnoMAOEFaDy2JO+TAsKwRXU8RcU1X0TdretnZYOrdMQJxSFBAmD0j0 B1HXOEW+W+AyOjFUOsB/WV24bM/XN9OHjsy37gO2x36t+j+GDcsjvIzpN GWENH3Trmk0AYhGKZVEji7B3V37s5MZW9Q6kVscq1Z5gJAkNCpZ3DqzAc LO1StXrnpnrx0GBn//ZTkmruVSZLV28V0fBjqjfgkvfQiKMNCl9PcTmfe w==; X-IronPort-AV: E=Sophos;i="5.96,193,1665471600"; d="scan'208";a="125074991" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Nov 2022 02:46:20 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 25 Nov 2022 02:46:16 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 25 Nov 2022 02:46:14 -0700 From: Horatiu Vultur To: , , CC: , , , , , , , , Horatiu Vultur Subject: [PATCH net-next 4/9] net: lan966x: Add is2 vcap model to vcap API. Date: Fri, 25 Nov 2022 10:50:05 +0100 Message-ID: <20221125095010.124458-5-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221125095010.124458-1-horatiu.vultur@microchip.com> References: <20221125095010.124458-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This provides the lan966x is2 model and adds it to the vcap control instance that will be provided to the vcap API. Signed-off-by: Horatiu Vultur --- .../net/ethernet/microchip/lan966x/Makefile | 2 +- .../microchip/lan966x/lan966x_vcap_ag_api.c | 1608 +++++++++++++++++ .../microchip/lan966x/lan966x_vcap_ag_api.h | 11 + .../microchip/lan966x/lan966x_vcap_impl.c | 4 + 4 files changed, 1624 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_= api.c create mode 100644 drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_= api.h diff --git a/drivers/net/ethernet/microchip/lan966x/Makefile b/drivers/net/= ethernet/microchip/lan966x/Makefile index 2c27784859014..053a174f09f32 100644 --- a/drivers/net/ethernet/microchip/lan966x/Makefile +++ b/drivers/net/ethernet/microchip/lan966x/Makefile @@ -12,7 +12,7 @@ lan966x-switch-objs :=3D lan966x_main.o lan966x_phylink.= o lan966x_port.o \ lan966x_tc.o lan966x_mqprio.o lan966x_taprio.o \ lan966x_tbf.o lan966x_cbs.o lan966x_ets.o \ lan966x_tc_matchall.o lan966x_police.o lan966x_mirror.o \ - lan966x_xdp.o lan966x_vcap_impl.o + lan966x_xdp.o lan966x_vcap_impl.o lan966x_vcap_ag_api.o =20 # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c b= /drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c new file mode 100644 index 0000000000000..928e711960e6b --- /dev/null +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c @@ -0,0 +1,1608 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include +#include + +#include "lan966x_vcap_ag_api.h" + +/* keyfields */ +static const struct vcap_field is2_mac_etype_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 43, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 91, + .width =3D 48, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 139, + .width =3D 16, + }, + [VCAP_KF_L2_FRM_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 155, + .width =3D 4, + }, + [VCAP_KF_L2_PAYLOAD0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 159, + .width =3D 16, + }, + [VCAP_KF_L2_PAYLOAD1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 175, + .width =3D 8, + }, + [VCAP_KF_L2_PAYLOAD2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 183, + .width =3D 3, + }, +}; + +static const struct vcap_field is2_mac_llc_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 43, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 91, + .width =3D 48, + }, + [VCAP_KF_L2_LLC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 139, + .width =3D 40, + }, +}; + +static const struct vcap_field is2_mac_snap_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 43, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 91, + .width =3D 48, + }, + [VCAP_KF_L2_SNAP] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 139, + .width =3D 40, + }, +}; + +static const struct vcap_field is2_arp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 43, + .width =3D 48, + }, + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 91, + .width =3D 1, + }, + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_ARP_LEN_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_ARP_TGT_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 97, + .width =3D 2, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 99, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 131, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 163, + .width =3D 1, + }, +}; + +static const struct vcap_field is2_ip4_tcp_udp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 43, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 44, + .width =3D 1, + }, + [VCAP_KF_L3_FRAG_OFS_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 45, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 46, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 47, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 48, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 120, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 121, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 122, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 138, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 154, + .width =3D 8, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 162, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 163, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 164, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 165, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 166, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 167, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 168, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 169, + .width =3D 1, + }, + [VCAP_KF_L4_1588_DOM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 170, + .width =3D 8, + }, + [VCAP_KF_L4_1588_VER] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 178, + .width =3D 4, + }, +}; + +static const struct vcap_field is2_ip4_other_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 43, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 44, + .width =3D 1, + }, + [VCAP_KF_L3_FRAG_OFS_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 45, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 46, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 47, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 48, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 120, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 121, + .width =3D 8, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U56, + .offset =3D 129, + .width =3D 56, + }, +}; + +static const struct vcap_field is2_ip6_std_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 43, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 44, + .width =3D 128, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 172, + .width =3D 8, + }, +}; + +static const struct vcap_field is2_oam_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 26, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 3, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 43, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 91, + .width =3D 48, + }, + [VCAP_KF_OAM_MEL_FLAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 139, + .width =3D 7, + }, + [VCAP_KF_OAM_VER] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 146, + .width =3D 5, + }, + [VCAP_KF_OAM_OPCODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 151, + .width =3D 8, + }, + [VCAP_KF_OAM_FLAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 159, + .width =3D 8, + }, + [VCAP_KF_OAM_MEPID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 167, + .width =3D 16, + }, + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 183, + .width =3D 1, + }, + [VCAP_KF_OAM_Y1731_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 184, + .width =3D 1, + }, + [VCAP_KF_OAM_DETECTED] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 185, + .width =3D 1, + }, +}; + +static const struct vcap_field is2_ip6_tcp_udp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 11, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 20, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 21, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 25, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 37, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 38, + .width =3D 3, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 41, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 8, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 50, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 178, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 306, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 307, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 308, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 324, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 340, + .width =3D 8, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 348, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 349, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 350, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 351, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 352, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 353, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 354, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 355, + .width =3D 1, + }, + [VCAP_KF_L4_1588_DOM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 356, + .width =3D 8, + }, + [VCAP_KF_L4_1588_VER] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 364, + .width =3D 4, + }, +}; + +static const struct vcap_field is2_ip6_other_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 11, + .width =3D 9, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 20, + .width =3D 1, + }, + [VCAP_KF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 21, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 22, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 24, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 25, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 37, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 38, + .width =3D 3, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 41, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 8, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 50, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 178, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 306, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 307, + .width =3D 8, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U56, + .offset =3D 315, + .width =3D 56, + }, +}; + +static const struct vcap_field is2_smac_sip4_keyfield[] =3D { + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 4, + .width =3D 48, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 52, + .width =3D 32, + }, +}; + +static const struct vcap_field is2_smac_sip6_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 4, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 8, + .width =3D 48, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 56, + .width =3D 128, + }, +}; + +/* keyfield_set */ +static const struct vcap_set is2_keyfield_set[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D { + .type_id =3D 0, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_MAC_LLC] =3D { + .type_id =3D 1, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_MAC_SNAP] =3D { + .type_id =3D 2, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_ARP] =3D { + .type_id =3D 3, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_TCP_UDP] =3D { + .type_id =3D 4, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_OTHER] =3D { + .type_id =3D 5, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP6_STD] =3D { + .type_id =3D 6, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_OAM] =3D { + .type_id =3D 7, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP6_TCP_UDP] =3D { + .type_id =3D 0, + .sw_per_item =3D 4, + .sw_cnt =3D 1, + }, + [VCAP_KFS_IP6_OTHER] =3D { + .type_id =3D 1, + .sw_per_item =3D 4, + .sw_cnt =3D 1, + }, + [VCAP_KFS_SMAC_SIP4] =3D { + .type_id =3D -1, + .sw_per_item =3D 1, + .sw_cnt =3D 4, + }, + [VCAP_KFS_SMAC_SIP6] =3D { + .type_id =3D 8, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, +}; + +/* keyfield_set map */ +static const struct vcap_field *is2_keyfield_set_map[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D is2_mac_etype_keyfield, + [VCAP_KFS_MAC_LLC] =3D is2_mac_llc_keyfield, + [VCAP_KFS_MAC_SNAP] =3D is2_mac_snap_keyfield, + [VCAP_KFS_ARP] =3D is2_arp_keyfield, + [VCAP_KFS_IP4_TCP_UDP] =3D is2_ip4_tcp_udp_keyfield, + [VCAP_KFS_IP4_OTHER] =3D is2_ip4_other_keyfield, + [VCAP_KFS_IP6_STD] =3D is2_ip6_std_keyfield, + [VCAP_KFS_OAM] =3D is2_oam_keyfield, + [VCAP_KFS_IP6_TCP_UDP] =3D is2_ip6_tcp_udp_keyfield, + [VCAP_KFS_IP6_OTHER] =3D is2_ip6_other_keyfield, + [VCAP_KFS_SMAC_SIP4] =3D is2_smac_sip4_keyfield, + [VCAP_KFS_SMAC_SIP6] =3D is2_smac_sip6_keyfield, +}; + +/* keyfield_set map sizes */ +static int is2_keyfield_set_map_size[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D ARRAY_SIZE(is2_mac_etype_keyfield), + [VCAP_KFS_MAC_LLC] =3D ARRAY_SIZE(is2_mac_llc_keyfield), + [VCAP_KFS_MAC_SNAP] =3D ARRAY_SIZE(is2_mac_snap_keyfield), + [VCAP_KFS_ARP] =3D ARRAY_SIZE(is2_arp_keyfield), + [VCAP_KFS_IP4_TCP_UDP] =3D ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), + [VCAP_KFS_IP4_OTHER] =3D ARRAY_SIZE(is2_ip4_other_keyfield), + [VCAP_KFS_IP6_STD] =3D ARRAY_SIZE(is2_ip6_std_keyfield), + [VCAP_KFS_OAM] =3D ARRAY_SIZE(is2_oam_keyfield), + [VCAP_KFS_IP6_TCP_UDP] =3D ARRAY_SIZE(is2_ip6_tcp_udp_keyfield), + [VCAP_KFS_IP6_OTHER] =3D ARRAY_SIZE(is2_ip6_other_keyfield), + [VCAP_KFS_SMAC_SIP4] =3D ARRAY_SIZE(is2_smac_sip4_keyfield), + [VCAP_KFS_SMAC_SIP6] =3D ARRAY_SIZE(is2_smac_sip6_keyfield), +}; + +/* actionfields */ +static const struct vcap_field is2_base_type_actionfield[] =3D { + [VCAP_AF_HIT_ME_ONCE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_CPU_COPY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_CPU_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 3, + }, + [VCAP_AF_MASK_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 2, + }, + [VCAP_AF_MIRROR_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 7, + .width =3D 1, + }, + [VCAP_AF_LRN_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 8, + .width =3D 1, + }, + [VCAP_AF_POLICE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_POLICE_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 9, + }, + [VCAP_AF_POLICE_VCAP_ONLY] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 19, + .width =3D 1, + }, + [VCAP_AF_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 8, + }, + [VCAP_AF_REW_OP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 16, + }, + [VCAP_AF_ISDX_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 44, + .width =3D 1, + }, + [VCAP_AF_ACL_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 6, + }, +}; + +static const struct vcap_field is2_smac_sip_actionfield[] =3D { + [VCAP_AF_CPU_COPY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_CPU_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 1, + .width =3D 3, + }, + [VCAP_AF_FWD_KILL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_AF_HOST_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 5, + .width =3D 1, + }, +}; + +/* actionfield_set */ +static const struct vcap_set is2_actionfield_set[] =3D { + [VCAP_AFS_BASE_TYPE] =3D { + .type_id =3D -1, + .sw_per_item =3D 2, + .sw_cnt =3D 2, + }, + [VCAP_AFS_SMAC_SIP] =3D { + .type_id =3D -1, + .sw_per_item =3D 1, + .sw_cnt =3D 4, + }, +}; + +/* actionfield_set map */ +static const struct vcap_field *is2_actionfield_set_map[] =3D { + [VCAP_AFS_BASE_TYPE] =3D is2_base_type_actionfield, + [VCAP_AFS_SMAC_SIP] =3D is2_smac_sip_actionfield, +}; + +/* actionfield_set map size */ +static int is2_actionfield_set_map_size[] =3D { + [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(is2_base_type_actionfield), + [VCAP_AFS_SMAC_SIP] =3D ARRAY_SIZE(is2_smac_sip_actionfield), +}; + +/* Type Groups */ +static const struct vcap_typegroup is2_x4_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 96, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 192, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 288, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x2_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 96, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 1, + .value =3D 1, + }, + {} +}; + +static const struct vcap_typegroup *is2_keyfield_set_typegroups[] =3D { + [4] =3D is2_x4_keyfield_set_typegroups, + [2] =3D is2_x2_keyfield_set_typegroups, + [1] =3D is2_x1_keyfield_set_typegroups, + [5] =3D NULL, +}; + +static const struct vcap_typegroup is2_x2_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 31, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 1, + .value =3D 1, + }, + {} +}; + +static const struct vcap_typegroup *is2_actionfield_set_typegroups[] =3D { + [2] =3D is2_x2_actionfield_set_typegroups, + [1] =3D is2_x1_actionfield_set_typegroups, + [5] =3D NULL, +}; + +/* Keyfieldset names */ +static const char * const vcap_keyfield_set_names[] =3D { + [VCAP_KFS_NO_VALUE] =3D "(None)", + [VCAP_KFS_ARP] =3D "VCAP_KFS_ARP", + [VCAP_KFS_IP4_OTHER] =3D "VCAP_KFS_IP4_OTHER", + [VCAP_KFS_IP4_TCP_UDP] =3D "VCAP_KFS_IP4_TCP_UDP", + [VCAP_KFS_IP6_OTHER] =3D "VCAP_KFS_IP6_OTHER", + [VCAP_KFS_IP6_STD] =3D "VCAP_KFS_IP6_STD", + [VCAP_KFS_IP6_TCP_UDP] =3D "VCAP_KFS_IP6_TCP_UDP", + [VCAP_KFS_MAC_ETYPE] =3D "VCAP_KFS_MAC_ETYPE", + [VCAP_KFS_MAC_LLC] =3D "VCAP_KFS_MAC_LLC", + [VCAP_KFS_MAC_SNAP] =3D "VCAP_KFS_MAC_SNAP", + [VCAP_KFS_OAM] =3D "VCAP_KFS_OAM", + [VCAP_KFS_SMAC_SIP4] =3D "VCAP_KFS_SMAC_SIP4", + [VCAP_KFS_SMAC_SIP6] =3D "VCAP_KFS_SMAC_SIP6", +}; + +/* Actionfieldset names */ +static const char * const vcap_actionfield_set_names[] =3D { + [VCAP_AFS_NO_VALUE] =3D "(None)", + [VCAP_AFS_BASE_TYPE] =3D "VCAP_AFS_BASE_TYPE", + [VCAP_AFS_SMAC_SIP] =3D "VCAP_AFS_SMAC_SIP", +}; + +/* Keyfield names */ +static const char * const vcap_keyfield_names[] =3D { + [VCAP_KF_NO_VALUE] =3D "(None)", + [VCAP_KF_8021Q_DEI_CLS] =3D "8021Q_DEI_CLS", + [VCAP_KF_8021Q_PCP_CLS] =3D "8021Q_PCP_CLS", + [VCAP_KF_8021Q_VID_CLS] =3D "8021Q_VID_CLS", + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D "8021Q_VLAN_TAGGED_IS", + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D "ARP_ADDR_SPACE_OK_IS", + [VCAP_KF_ARP_LEN_OK_IS] =3D "ARP_LEN_OK_IS", + [VCAP_KF_ARP_OPCODE] =3D "ARP_OPCODE", + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D "ARP_OPCODE_UNKNOWN_IS", + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D "ARP_PROTO_SPACE_OK_IS", + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D "ARP_SENDER_MATCH_IS", + [VCAP_KF_ARP_TGT_MATCH_IS] =3D "ARP_TGT_MATCH_IS", + [VCAP_KF_ETYPE] =3D "ETYPE", + [VCAP_KF_HOST_MATCH] =3D "HOST_MATCH", + [VCAP_KF_IF_IGR_PORT] =3D "IF_IGR_PORT", + [VCAP_KF_IF_IGR_PORT_MASK] =3D "IF_IGR_PORT_MASK", + [VCAP_KF_IP4_IS] =3D "IP4_IS", + [VCAP_KF_ISDX_GT0_IS] =3D "ISDX_GT0_IS", + [VCAP_KF_L2_BC_IS] =3D "L2_BC_IS", + [VCAP_KF_L2_DMAC] =3D "L2_DMAC", + [VCAP_KF_L2_FRM_TYPE] =3D "L2_FRM_TYPE", + [VCAP_KF_L2_LLC] =3D "L2_LLC", + [VCAP_KF_L2_MC_IS] =3D "L2_MC_IS", + [VCAP_KF_L2_PAYLOAD0] =3D "L2_PAYLOAD0", + [VCAP_KF_L2_PAYLOAD1] =3D "L2_PAYLOAD1", + [VCAP_KF_L2_PAYLOAD2] =3D "L2_PAYLOAD2", + [VCAP_KF_L2_SMAC] =3D "L2_SMAC", + [VCAP_KF_L2_SNAP] =3D "L2_SNAP", + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D "L3_DIP_EQ_SIP_IS", + [VCAP_KF_L3_FRAGMENT] =3D "L3_FRAGMENT", + [VCAP_KF_L3_FRAG_OFS_GT0] =3D "L3_FRAG_OFS_GT0", + [VCAP_KF_L3_IP4_DIP] =3D "L3_IP4_DIP", + [VCAP_KF_L3_IP4_SIP] =3D "L3_IP4_SIP", + [VCAP_KF_L3_IP6_DIP] =3D "L3_IP6_DIP", + [VCAP_KF_L3_IP6_SIP] =3D "L3_IP6_SIP", + [VCAP_KF_L3_IP_PROTO] =3D "L3_IP_PROTO", + [VCAP_KF_L3_OPTIONS_IS] =3D "L3_OPTIONS_IS", + [VCAP_KF_L3_PAYLOAD] =3D "L3_PAYLOAD", + [VCAP_KF_L3_TOS] =3D "L3_TOS", + [VCAP_KF_L3_TTL_GT0] =3D "L3_TTL_GT0", + [VCAP_KF_L4_1588_DOM] =3D "L4_1588_DOM", + [VCAP_KF_L4_1588_VER] =3D "L4_1588_VER", + [VCAP_KF_L4_ACK] =3D "L4_ACK", + [VCAP_KF_L4_DPORT] =3D "L4_DPORT", + [VCAP_KF_L4_FIN] =3D "L4_FIN", + [VCAP_KF_L4_PSH] =3D "L4_PSH", + [VCAP_KF_L4_RNG] =3D "L4_RNG", + [VCAP_KF_L4_RST] =3D "L4_RST", + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D "L4_SEQUENCE_EQ0_IS", + [VCAP_KF_L4_SPORT] =3D "L4_SPORT", + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D "L4_SPORT_EQ_DPORT_IS", + [VCAP_KF_L4_SYN] =3D "L4_SYN", + [VCAP_KF_L4_URG] =3D "L4_URG", + [VCAP_KF_LOOKUP_FIRST_IS] =3D "LOOKUP_FIRST_IS", + [VCAP_KF_LOOKUP_PAG] =3D "LOOKUP_PAG", + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D "OAM_CCM_CNTS_EQ0", + [VCAP_KF_OAM_DETECTED] =3D "OAM_DETECTED", + [VCAP_KF_OAM_FLAGS] =3D "OAM_FLAGS", + [VCAP_KF_OAM_MEL_FLAGS] =3D "OAM_MEL_FLAGS", + [VCAP_KF_OAM_MEPID] =3D "OAM_MEPID", + [VCAP_KF_OAM_OPCODE] =3D "OAM_OPCODE", + [VCAP_KF_OAM_VER] =3D "OAM_VER", + [VCAP_KF_OAM_Y1731_IS] =3D "OAM_Y1731_IS", + [VCAP_KF_TCP_IS] =3D "TCP_IS", + [VCAP_KF_TYPE] =3D "TYPE", +}; + +/* Actionfield names */ +static const char * const vcap_actionfield_names[] =3D { + [VCAP_AF_NO_VALUE] =3D "(None)", + [VCAP_AF_ACL_ID] =3D "ACL_ID", + [VCAP_AF_CPU_COPY_ENA] =3D "CPU_COPY_ENA", + [VCAP_AF_CPU_QUEUE_NUM] =3D "CPU_QUEUE_NUM", + [VCAP_AF_FWD_KILL_ENA] =3D "FWD_KILL_ENA", + [VCAP_AF_HIT_ME_ONCE] =3D "HIT_ME_ONCE", + [VCAP_AF_HOST_MATCH] =3D "HOST_MATCH", + [VCAP_AF_ISDX_ENA] =3D "ISDX_ENA", + [VCAP_AF_LRN_DIS] =3D "LRN_DIS", + [VCAP_AF_MASK_MODE] =3D "MASK_MODE", + [VCAP_AF_MIRROR_ENA] =3D "MIRROR_ENA", + [VCAP_AF_POLICE_ENA] =3D "POLICE_ENA", + [VCAP_AF_POLICE_IDX] =3D "POLICE_IDX", + [VCAP_AF_POLICE_VCAP_ONLY] =3D "POLICE_VCAP_ONLY", + [VCAP_AF_PORT_MASK] =3D "PORT_MASK", + [VCAP_AF_REW_OP] =3D "REW_OP", +}; + +/* VCAPs */ +const struct vcap_info lan966x_vcaps[] =3D { + [VCAP_TYPE_IS2] =3D { + .name =3D "is2", + .rows =3D 64, + .sw_count =3D 4, + .sw_width =3D 96, + .sticky_width =3D 32, + .act_width =3D 31, + .default_cnt =3D 11, + .require_cnt_dis =3D 1, + .version =3D 1, + .keyfield_set =3D is2_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(is2_keyfield_set), + .actionfield_set =3D is2_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(is2_actionfield_set), + .keyfield_set_map =3D is2_keyfield_set_map, + .keyfield_set_map_size =3D is2_keyfield_set_map_size, + .actionfield_set_map =3D is2_actionfield_set_map, + .actionfield_set_map_size =3D is2_actionfield_set_map_size, + .keyfield_set_typegroups =3D is2_keyfield_set_typegroups, + .actionfield_set_typegroups =3D is2_actionfield_set_typegroups, + }, +}; + +const struct vcap_statistics lan966x_vcap_stats =3D { + .name =3D "lan966x", + .count =3D 1, + .keyfield_set_names =3D vcap_keyfield_set_names, + .actionfield_set_names =3D vcap_actionfield_set_names, + .keyfield_names =3D vcap_keyfield_names, + .actionfield_names =3D vcap_actionfield_names, +}; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.h b= /drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.h new file mode 100644 index 0000000000000..0d8bbee73b2a5 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __LAN966X_VCAP_AG_API_H__ +#define __LAN966X_VCAP_AG_API_H__ + +#include "vcap_api.h" + +extern const struct vcap_info lan966x_vcaps[]; +extern const struct vcap_statistics lan966x_vcap_stats; + +#endif /* __LAN966X_VCAP_AG_API_H__ */ diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c b/d= rivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c index 8d89cfcb8502d..aac821cd611e8 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ =20 #include "lan966x_main.h" +#include "lan966x_vcap_ag_api.h" #include "vcap_api.h" =20 int lan966x_vcap_init(struct lan966x *lan966x) @@ -11,6 +12,9 @@ int lan966x_vcap_init(struct lan966x *lan966x) if (!ctrl) return -ENOMEM; =20 + ctrl->vcaps =3D lan966x_vcaps; + ctrl->stats =3D &lan966x_vcap_stats; + lan966x->vcap_ctrl =3D ctrl; =20 return 0; --=20 2.38.0