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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT086.mail.protection.outlook.com (10.13.173.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5834.8 via Frontend Transport; Fri, 25 Nov 2022 03:21:07 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 24 Nov 2022 21:20:39 -0600 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH] perf test: Add event group test Date: Fri, 25 Nov 2022 08:50:18 +0530 Message-ID: <20221125032018.962-1-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT086:EE_|SJ0PR12MB5453:EE_ X-MS-Office365-Filtering-Correlation-Id: bf23b3ea-41b9-4cd1-23a2-08dace941780 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2022 03:21:07.0320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf23b3ea-41b9-4cd1-23a2-08dace941780 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT086.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5453 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Multiple events in a group can belong to one or more pmus, however there are some limitations to it. Basically, perf doesn't allow creating a group of events from different hw pmus. Write a simple test to create various combinations of hw, sw and uncore pmu events and verify group creation succeeds or fails as expected. Signed-off-by: Ravi Bangoria --- Note: Uncore pmu event detail for Intel, Arm, PowerPC and s390 needs to be verified/fixed. These are marked as XXX in the patch. tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test.c | 1 + tools/perf/tests/event_groups.c | 126 ++++++++++++++++++++++++++++++++ tools/perf/tests/tests.h | 1 + 4 files changed, 129 insertions(+) create mode 100644 tools/perf/tests/event_groups.c diff --git a/tools/perf/tests/Build b/tools/perf/tests/Build index 2064a640facb..9a59d451ca44 100644 --- a/tools/perf/tests/Build +++ b/tools/perf/tests/Build @@ -67,6 +67,7 @@ perf-y +=3D expand-cgroup.o perf-y +=3D perf-time-to-tsc.o perf-y +=3D dlfilter-test.o perf-y +=3D sigtrap.o +perf-y +=3D event_groups.o =20 $(OUTPUT)tests/llvm-src-base.c: tests/bpf-script-example.c tests/Build $(call rule_mkdir) diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-tes= t.c index 7122eae1d98d..48cd0c809cb1 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -110,6 +110,7 @@ static struct test_suite *generic_tests[] =3D { &suite__perf_time_to_tsc, &suite__dlfilter, &suite__sigtrap, + &suite__event_groups, NULL, }; =20 diff --git a/tools/perf/tests/event_groups.c b/tools/perf/tests/event_group= s.c new file mode 100644 index 000000000000..92486b68cadb --- /dev/null +++ b/tools/perf/tests/event_groups.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include "linux/perf_event.h" +#include "tests.h" +#include "debug.h" +#include "pmu.h" +#include "header.h" +#include "../perf-sys.h" + +static int event_open(int type, unsigned long config, int g_fd) +{ + struct perf_event_attr attr; + + memset(&attr, 0, sizeof(struct perf_event_attr)); + attr.type =3D type; + attr.size =3D sizeof(struct perf_event_attr); + attr.config =3D config; + attr.disabled =3D g_fd =3D=3D -1 ? 1 : 0; + + return sys_perf_event_open(&attr, -1, 0, g_fd, 0); +} + +/* hw: cycles, sw: context-switch, uncore: [arch dependent] */ +int type[] =3D {0, 1, -1}; +unsigned long config[] =3D {0, 3, -1}; + +static int setup_uncore_event(void) +{ + char pmu_name[25] =3D {0}; + struct perf_pmu *pmu; + +#if defined(__x86_64__) || defined(__i386__) +{ + char buf[128] =3D {0}; + + if (get_cpuid(buf, sizeof(buf))) + return -1; + if (strstr(buf, "Intel")) { + strcpy(pmu_name, "uncore_imc_0"); /* XXX */ + config[2] =3D 0xff04; + } else { + strcpy(pmu_name, "amd_l3"); + config[2] =3D 0xff04; /* l3_cache_accesses */ + } +} +#elif defined(__arm__) || defined(__aarch64__) + strcpy(pmu_name, "l2c_220"); /* XXX */ + config[2] =3D 0x0; +#elif defined(__powerpc__) + strcpy(pmu_name, "hv_24x7"); /* XXX */ + config[2] =3D 0x0; +#elif defined(__s390x__) + strcpy(pmu_name, "pai_crypto"); /* XXX */ + config[2] =3D 0x0; +#else + pr_debug("No uncore pmu event found\n"); + return -1; +#endif + + pmu =3D perf_pmu__find(pmu_name); + if (!pmu) { + pr_debug("Can not find uncore pmu\n"); + return -1; + } + type[2] =3D pmu->type; + return 0; +} + +static int run_test(int i, int j, int k) +{ + int erroneous =3D ((((1 << i) | (1 << j) | (1 << k)) & 5) =3D=3D 5); + int fd1, fd2, fd3; + + fd1 =3D event_open(type[i], config[i], -1); + if (fd1 =3D=3D -1) + return -1; + + fd2 =3D event_open(type[j], config[j], fd1); + if (fd2 =3D=3D -1) { + close(fd1); + return erroneous ? 0 : -1; + } + + fd3 =3D event_open(type[k], config[k], fd1); + if (fd3 =3D=3D -1) { + close(fd1); + close(fd2); + return erroneous ? 0 : -1; + } + + close(fd1); + close(fd2); + close(fd3); + return erroneous ? -1 : 0; +} + +static int test__event_groups(struct test_suite *text __maybe_unused, int = subtest __maybe_unused) +{ + int i, j, k; + int ret; + int r; + + ret =3D setup_uncore_event(); + if (ret || type[2] =3D=3D -1) + return TEST_SKIP; + + ret =3D TEST_OK; + for (i =3D 0; i < 3; i++) { + for (j =3D 0; j < 3; j++) { + for (k =3D 0; k < 3; k++) { + r =3D run_test(i, j, k); + if (r) + ret =3D TEST_FAIL; + + pr_debug("0x%x 0x%lx, 0x%x 0x%lx, 0x%x 0x%lx: %s\n", + type[i], config[i], type[j], config[j], + type[k], config[k], r ? "Fail" : "Pass"); + } + } + } + return ret; +} + +DEFINE_SUITE("Event groups", event_groups); diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h index 5bbb8f6a48fc..08570b5505d7 100644 --- a/tools/perf/tests/tests.h +++ b/tools/perf/tests/tests.h @@ -147,6 +147,7 @@ DECLARE_SUITE(expand_cgroup_events); DECLARE_SUITE(perf_time_to_tsc); DECLARE_SUITE(dlfilter); DECLARE_SUITE(sigtrap); +DECLARE_SUITE(event_groups); =20 /* * PowerPC and S390 do not support creation of instruction breakpoints usi= ng the --=20 2.38.1