From nobody Wed Apr 24 04:58:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7557DC433FE for ; Thu, 24 Nov 2022 14:49:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229821AbiKXOt4 (ORCPT ); Thu, 24 Nov 2022 09:49:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229612AbiKXOth (ORCPT ); Thu, 24 Nov 2022 09:49:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF35CFF426; Thu, 24 Nov 2022 06:49:33 -0800 (PST) Received: from jupiter.universe (dyndsl-095-033-156-095.ewe-ip-backbone.de [95.33.156.95]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id B50DF6602B35; Thu, 24 Nov 2022 14:49:31 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669301371; bh=viiw6iEQ5QEwitVPLI34wwFzRnaLWqS25MPHuNwil24=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jcz9xKfMblEKKRV/aGLrdVBGnpN3IDuEKrW7r5/28du5PliWWC4CD0pmQtBHeKZzy I8rcIfcRU+nc2oEvuiYsZ42KcvIjaxQpaMeEMiPm3xwN2BymslIknJYjzBkyVxwjcU cWevMJUdcd+vMtfFvzm/g7BiMzQGKCzHdIS9EICEvhQz7oLYNiKtl1G13QtCBexTrj 4glxOMX0IshStr11+EBvMDlIHP/d7Iwd71qqCxekU/ZkISZxC8smVywilD14htSyOb ZR2XYR+Sk5LVN2PgkrAQ5RJOOghMRE+841KYuxx6j5BIae7i0taFX3cc/GHtk579HT 77bQTj7NOLTzg== Received: by jupiter.universe (Postfix, from userid 1000) id 60BDE48011C; Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kever Yang , kernel@collabora.com, Yifeng Zhao , Elaine Zhang , Sugar Zhang , Sebastian Reichel Subject: [PATCHv4 3/7] arm64: dts: rockchip: Add base DT for rk3588 SoC Date: Thu, 24 Nov 2022 15:49:24 +0100 Message-Id: <20221124144928.35381-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kever Yang This initial version supports (single core) CPU, dma, interrupts, timers, UART and SDHCI. In short - everything necessary to boot Linux on this system on chip. The DT is split into rk3588 and rk3588s, which is a reduced version (i.e. with less peripherals) of the former. Signed-off-by: Yifeng Zhao Signed-off-by: Elaine Zhang Signed-off-by: Sugar Zhang Signed-off-by: Kever Yang [rebase, squash and reword commit message] Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 58 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1672 +++++++++++++++++++++ 2 files changed, 1730 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi new file mode 100644 index 000000000000..3948597fc8ec --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588s.dtsi" +#include "rk3588-pinctrl.dtsi" + +/ { + gmac0: ethernet@fe1b0000 { + compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg =3D <0x0 0xfe1b0000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_wake_irq"; + clocks =3D <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru CLK_GMAC0_PTP_REF>; + clock-names =3D "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains =3D <&power RK3588_PD_GMAC>; + resets =3D <&cru SRST_A_GMAC0>; + reset-names =3D "stmmaceth"; + rockchip,grf =3D <&sys_grf>; + rockchip,php-grf =3D <&php_grf>; + snps,axi-config =3D <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config =3D <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac0_mtl_tx_setup>; + snps,tso; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,wr_osr_lmt =3D <4>; + snps,rd_osr_lmt =3D <8>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi new file mode 100644 index 000000000000..ecdd2294cd42 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -0,0 +1,1672 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include + +/ { + compatible =3D "rockchip,rk3588"; + + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_l0>; + }; + core1 { + cpu =3D <&cpu_l1>; + }; + core2 { + cpu =3D <&cpu_l2>; + }; + core3 { + cpu =3D <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu =3D <&cpu_b0>; + }; + core1 { + cpu =3D <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu =3D <&cpu_b2>; + }; + core1 { + cpu =3D <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l0>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_l1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l1>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_l2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l2>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_l3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l3>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_b0: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x400>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b0>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + cpu_b1: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x500>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b1>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + cpu_b2: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x600>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b2>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + cpu_b3: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x700>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b3>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + idle-states { + entry-method =3D "psci"; + CPU_SLEEP: cpu-sleep { + compatible =3D "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param =3D <0x0010000>; + entry-latency-us =3D <100>; + exit-latency-us =3D <120>; + min-residency-us =3D <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible =3D "cache"; + cache-size =3D <3145728>; + cache-line-size =3D <64>; + cache-sets =3D <4096>; + }; + }; + + firmware { + optee: optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000010>; + shmem =3D <&scmi_shmem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB01>, + <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates =3D <1200000000>, + <1200000000>; + #clock-cells =3D <1>; + }; + + scmi_reset: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + pmu-a76 { + compatible =3D "arm,cortex-a76-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + spll: clock-0 { + compatible =3D "fixed-clock"; + clock-frequency =3D <702000000>; + clock-output-names =3D "spll"; + #clock-cells =3D <0>; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + xin24m: clock-1 { + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "xin24m"; + #clock-cells =3D <0>; + }; + + xin32k: clock-2 { + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "xin32k"; + #clock-cells =3D <0>; + }; + + pmu_sram: sram@10f000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x0010f000 0x0 0x100>; + ranges =3D <0 0x0 0x0010f000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + scmi_shmem: sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + }; + + sys_grf: syscon@fd58c000 { + compatible =3D "rockchip,rk3588-sys-grf", "syscon"; + reg =3D <0x0 0xfd58c000 0x0 0x1000>; + }; + + php_grf: syscon@fd5b0000 { + compatible =3D "rockchip,rk3588-php-grf", "syscon"; + reg =3D <0x0 0xfd5b0000 0x0 0x1000>; + }; + + ioc: syscon@fd5f0000 { + compatible =3D "rockchip,rk3588-ioc", "syscon"; + reg =3D <0x0 0xfd5f0000 0x0 0x10000>; + }; + + system_sram1: sram@fd600000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xfd600000 0x0 0x100000>; + ranges =3D <0x0 0x0 0xfd600000 0x100000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + cru: clock-controller@fd7c0000 { + compatible =3D "rockchip,rk3588-cru"; + reg =3D <0x0 0xfd7c0000 0x0 0x5c000>; + assigned-clocks =3D + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>; + assigned-clock-rates =3D + <100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <800000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, <500000000>, + <375000000>, <150000000>, + <200000000>; + rockchip,grf =3D <&php_grf>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + i2c0: i2c@fd880000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfd880000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names =3D "i2c", "pclk"; + pinctrl-0 =3D <&i2c0m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@fd890000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfd890000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 6>, <&dmac0 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart0m1_xfer>; + pinctrl-names =3D "default"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0000 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm0m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0010 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm1m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0020 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm2m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0030 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm3m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible =3D "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg =3D <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible =3D "rockchip,rk3588-power-controller"; + #address-cells =3D <1>; + #power-domain-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_NPUTOP { + reg =3D ; + clocks =3D <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>, + <&cru HCLK_NPU_CM0_ROOT>; + pm_qos =3D <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_NPU1 { + reg =3D ; + clocks =3D <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos =3D <&qos_npu1>; + }; + power-domain@RK3588_PD_NPU2 { + reg =3D ; + clocks =3D <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos =3D <&qos_npu2>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg =3D ; + clocks =3D <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + pm_qos =3D <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>, + <&cru ACLK_RKVDEC_CCU>; + pm_qos =3D <&qos_rkvdec0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC1>; + pm_qos =3D <&qos_rkvdec1>; + }; + power-domain@RK3588_PD_VENC0 { + reg =3D ; + clocks =3D <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>; + pm_qos =3D <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_VENC1 { + reg =3D ; + clocks =3D <&cru HCLK_RKVENC1>, + <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>, + <&cru ACLK_RKVENC1>; + pm_qos =3D <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg =3D ; + clocks =3D <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_LOW_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_JPEG_DECODER_ROOT>, + <&cru ACLK_IEP2P0>, + <&cru HCLK_IEP2P0>, + <&cru ACLK_JPEG_ENCODER0>, + <&cru HCLK_JPEG_ENCODER0>, + <&cru ACLK_JPEG_ENCODER1>, + <&cru HCLK_JPEG_ENCODER1>, + <&cru ACLK_JPEG_ENCODER2>, + <&cru HCLK_JPEG_ENCODER2>, + <&cru ACLK_JPEG_ENCODER3>, + <&cru HCLK_JPEG_ENCODER3>, + <&cru ACLK_JPEG_DECODER>, + <&cru HCLK_JPEG_DECODER>, + <&cru ACLK_RGA2>, + <&cru HCLK_RGA2>; + pm_qos =3D <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + + power-domain@RK3588_PD_AV1 { + reg =3D ; + clocks =3D <&cru PCLK_AV1>, + <&cru ACLK_AV1>, + <&cru HCLK_VDPU_ROOT>; + pm_qos =3D <&qos_av1>; + }; + power-domain@RK3588_PD_RKVDEC0 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>; + pm_qos =3D <&qos_rkvdec0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>; + pm_qos =3D <&qos_rkvdec1>; + }; + power-domain@RK3588_PD_RGA30 { + reg =3D ; + clocks =3D <&cru ACLK_RGA3_0>, + <&cru HCLK_RGA3_0>; + pm_qos =3D <&qos_rga3_0>; + }; + }; + power-domain@RK3588_PD_VOP { + reg =3D ; + clocks =3D <&cru PCLK_VOP_ROOT>, + <&cru HCLK_VOP_ROOT>, + <&cru ACLK_VOP>; + pm_qos =3D <&qos_vop_m0>, + <&qos_vop_m1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_VO0 { + reg =3D ; + clocks =3D <&cru PCLK_VO0_ROOT>, + <&cru PCLK_VO0_S_ROOT>, + <&cru HCLK_VO0_S_ROOT>, + <&cru ACLK_VO0_ROOT>, + <&cru HCLK_HDCP0>, + <&cru ACLK_HDCP0>, + <&cru HCLK_VOP_ROOT>; + pm_qos =3D <&qos_hdcp0>; + }; + }; + power-domain@RK3588_PD_VO1 { + reg =3D ; + clocks =3D <&cru PCLK_VO1_ROOT>, + <&cru PCLK_VO1_S_ROOT>, + <&cru HCLK_VO1_S_ROOT>, + <&cru HCLK_HDCP1>, + <&cru ACLK_HDCP1>, + <&cru ACLK_HDMIRX_ROOT>, + <&cru HCLK_VO1USB_TOP_ROOT>; + pm_qos =3D <&qos_hdcp1>, + <&qos_hdmirx>; + }; + power-domain@RK3588_PD_VI { + reg =3D ; + clocks =3D <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>, + <&cru HCLK_ISP0>, + <&cru ACLK_ISP0>, + <&cru HCLK_VICAP>, + <&cru ACLK_VICAP>; + pm_qos =3D <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_ISP1 { + reg =3D ; + clocks =3D <&cru HCLK_ISP1>, + <&cru ACLK_ISP1>, + <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>; + pm_qos =3D <&qos_isp1_mwo>, + <&qos_isp1_mro>; + }; + power-domain@RK3588_PD_FEC { + reg =3D ; + clocks =3D <&cru HCLK_FISHEYE0>, + <&cru ACLK_FISHEYE0>, + <&cru HCLK_FISHEYE1>, + <&cru ACLK_FISHEYE1>, + <&cru PCLK_VI_ROOT>; + pm_qos =3D <&qos_fisheye0>, + <&qos_fisheye1>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg =3D ; + clocks =3D <&cru HCLK_RGA3_1>, + <&cru ACLK_RGA3_1>; + pm_qos =3D <&qos_rga3_1>; + }; + power-domain@RK3588_PD_USB { + reg =3D ; + clocks =3D <&cru PCLK_PHP_ROOT>, + <&cru ACLK_USB_ROOT>, + <&cru HCLK_USB_ROOT>, + <&cru HCLK_HOST0>, + <&cru HCLK_HOST_ARB0>, + <&cru HCLK_HOST1>, + <&cru HCLK_HOST_ARB1>; + pm_qos =3D <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + }; + power-domain@RK3588_PD_GMAC { + reg =3D ; + clocks =3D <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + }; + power-domain@RK3588_PD_PCIE { + reg =3D ; + clocks =3D <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + }; + power-domain@RK3588_PD_SDIO { + reg =3D ; + clocks =3D <&cru HCLK_SDIO>, + <&cru HCLK_NVM_ROOT>; + pm_qos =3D <&qos_sdio>; + }; + power-domain@RK3588_PD_AUDIO { + reg =3D ; + clocks =3D <&cru HCLK_AUDIO_ROOT>, + <&cru PCLK_AUDIO_ROOT>; + }; + power-domain@RK3588_PD_SDMMC { + reg =3D ; + pm_qos =3D <&qos_sdmmc>; + }; + }; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf82200 0x0 0x20>; + }; + + gmac1: ethernet@fe1c0000 { + compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg =3D <0x0 0xfe1c0000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_wake_irq"; + clocks =3D <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru CLK_GMAC1_PTP_REF>; + clock-names =3D "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains =3D <&power RK3588_PD_GMAC>; + resets =3D <&cru SRST_A_GMAC1>; + reset-names =3D "stmmaceth"; + rockchip,grf =3D <&sys_grf>; + rockchip,php-grf =3D <&php_grf>; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + snps,tso; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,wr_osr_lmt =3D <4>; + snps,rd_osr_lmt =3D <8>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + }; + + sdhci: mmc@fe2e0000 { + compatible =3D "rockchip,rk3588-dwcmshc"; + reg =3D <0x0 0xfe2e0000 0x0 0x10000>; + interrupts =3D ; + assigned-clocks =3D <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC= >; + assigned-clock-rates =3D <200000000>, <24000000>, <200000000>; + clocks =3D <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names =3D "core", "bus", "axi", "block", "timer"; + max-frequency =3D <200000000>; + resets =3D <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names =3D "core", "bus", "axi", "block", "timer"; + status =3D "disabled"; + }; + + gic: interrupt-controller@fe600000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts =3D ; + interrupt-controller; + mbi-alias =3D <0x0 0xfe610000>; + mbi-ranges =3D <424 56>; + msi-controller; + #interrupt-cells =3D <3>; + + ppi-partitions { + interrupt-partition-0 { + affinity =3D < + &cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3 + &cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3 + >; + }; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xfea10000 0x0 0x4000>; + interrupts =3D , + ; + arm,pl330-periph-burst; + clocks =3D <&cru ACLK_DMAC0>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + }; + + dmac1: dma-controller@fea30000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xfea30000 0x0 0x4000>; + interrupts =3D , + ; + arm,pl330-periph-burst; + clocks =3D <&cru ACLK_DMAC1>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + }; + + i2c1: i2c@fea90000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfea90000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c1m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeaa0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c2m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeab0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c3m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeac0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c4m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfead0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c5m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@feb00000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb00000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac0 14>, <&dmac0 15>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@feb10000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb10000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac0 16>, <&dmac0 17>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@feb20000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb20000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac1 15>, <&dmac1 16>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@feb30000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb30000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac1 17>, <&dmac1 18>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart1: serial@feb40000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb40000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 8>, <&dmac0 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart1m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart2: serial@feb50000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb50000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 10>, <&dmac0 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart2m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart3: serial@feb60000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb60000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 12>, <&dmac0 13>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart3m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart4: serial@feb70000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb70000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac1 9>, <&dmac1 10>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart4m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart5: serial@feb80000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb80000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac1 11>, <&dmac1 12>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart5m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart6: serial@feb90000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb90000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac1 13>, <&dmac1 14>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart6m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart7: serial@feba0000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeba0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac2 7>, <&dmac2 8>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart7m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart8: serial@febb0000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfebb0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac2 9>, <&dmac2 10>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart8m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart9: serial@febc0000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfebc0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac2 11>, <&dmac2 12>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart9m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0000 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm4m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0010 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm5m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0020 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm6m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0030 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm7m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0000 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm8m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0010 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm9m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0020 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm10m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0030 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm11m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0000 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm12m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0010 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm13m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0020 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm14m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0030 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm15m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfec80000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c6m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfec90000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c7m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeca0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c8m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi4: spi@fecb0000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfecb0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac2 13>, <&dmac2 14>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + dmac2: dma-controller@fed10000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xfed10000 0x0 0x4000>; + interrupts =3D , + ; + arm,pl330-periph-burst; + clocks =3D <&cru ACLK_DMAC2>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + }; + + system_sram2: sram@ff001000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xff001000 0x0 0xef000>; + ranges =3D <0x0 0x0 0xff001000 0xef000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + pinctrl: pinctrl { + compatible =3D "rockchip,rk3588-pinctrl"; + ranges; + rockchip,grf =3D <&ioc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gpio0: gpio@fd8a0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfd8a0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@fec20000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec20000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@fec30000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec30000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@fec40000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec40000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 96 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio4: gpio@fec50000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec50000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 128 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + }; +}; + +#include "rk3588s-pinctrl.dtsi" --=20 2.38.1