From nobody Sat Jul 27 04:38:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD98AC352A1 for ; Thu, 24 Nov 2022 14:49:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229769AbiKXOto (ORCPT ); Thu, 24 Nov 2022 09:49:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229507AbiKXOtf (ORCPT ); Thu, 24 Nov 2022 09:49:35 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE8D8E0740; Thu, 24 Nov 2022 06:49:33 -0800 (PST) Received: from jupiter.universe (dyndsl-095-033-156-095.ewe-ip-backbone.de [95.33.156.95]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id AB4636602B33; Thu, 24 Nov 2022 14:49:31 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669301371; bh=qlnzhQ44iCK3pxL9XYC8nPs32bPPQp/Y7GvWZaFXzdk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MIjVS7Nsr9bSLu4kpYViFrNB+THuCpypYnqAdsy4Ue2+ij4JNZlmgd3Upwc95gOLf fUfO/9X6VJrYSGgg8cW9BN96n9oGSb3DPaa00glUfLyrhslsyqS926RNQycJTMQKJc je1xTN1lTLw3v9XqqV2Sr102ZZUjpk2EhUgJWM/iPwAaFVNmzWIijdvyOAuVPzN7a8 3ue7FIIxUhiL0j4Td8zyBl6F8Rn0BST+nao93WwD1dnpDnjZB4w8wMDLY4Aevphdu6 0C1F+Zw+cVaYFmgqZGrvkx64ykqaVrtzsVm5T/gYCh4zQYaTo2JS+Ficka/sOu3Xrk Y1DX1LrjIdVIw== Received: by jupiter.universe (Postfix, from userid 1000) id 59BC3480116; Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, Rob Herring Subject: [PATCHv4 1/7] dt-bindings: soc: rockchip: add initial rk3588 syscon compatibles Date: Thu, 24 Nov 2022 15:49:22 +0100 Message-Id: <20221124144928.35381-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add IOC and PHP GRF syscon compatibles for RK3588. Acked-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index 2ed8cca79b59..e682b407a383 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -20,6 +20,11 @@ properties: - rockchip,rk3568-pipe-grf - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-bigcore0-grf + - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-ioc + - rockchip,rk3588-php-grf + - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf --=20 2.38.1 From nobody Sat Jul 27 04:38:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C24FAC433FE for ; Thu, 24 Nov 2022 14:50:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229828AbiKXOuD (ORCPT ); Thu, 24 Nov 2022 09:50:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229629AbiKXOth (ORCPT ); Thu, 24 Nov 2022 09:49:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF5F510AD37; Thu, 24 Nov 2022 06:49:33 -0800 (PST) Received: from jupiter.universe (dyndsl-095-033-156-095.ewe-ip-backbone.de [95.33.156.95]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id B93246602B36; Thu, 24 Nov 2022 14:49:31 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669301371; bh=CeInrhbNM5/6iRSQLFVDMv0/76q4TDBfHSFYBldMwtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gHPv/9kZydqOEo66ugfO0WCvL+fXeOMOaP+x1/jI+Za3nLRmSHpOSMss7EaivLBDK 2PwwQvN5kh1rqBn1jPUGT9vBApOzHM/VV0Hi9eGL4BLs+NN/ddQRHcdq61DQT6Ds5K lT3sxISmSXFd5a5+XMlavKAOdc0LR7T+Qa49ViP2Az7OTnsdbcqhW5a3wWTKuTpQfI W7gXt/YSwrQLzRcDduD6iUhOuA3ppZGFIPX4erE+rDfFQjkiVz4QrxCqVkusg7JwKr Y+Sw2oq1lG4vAPDwh/ffSRJ7xtw/NGgTcni1HcXyD5xhVdJooMp0d+jH2cDCUXrncz SdE/FDGOyP+/Q== Received: by jupiter.universe (Postfix, from userid 1000) id 5DDB448011B; Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jianqun Xu , kernel@collabora.com, Shengfei Xu , Damon Ding , Steven Liu , Jon Lin , Finley Xiao , Sebastian Reichel Subject: [PATCHv4 2/7] arm64: dts: rockchip: Add rk3588 pinctrl data Date: Thu, 24 Nov 2022 15:49:23 +0100 Message-Id: <20221124144928.35381-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jianqun Xu This adds the pin controller data for rk3588 and rk3588s. Signed-off-by: Shengfei Xu Signed-off-by: Damon Ding Signed-off-by: Steven Liu Signed-off-by: Jon Lin Signed-off-by: Finley Xiao Signed-off-by: Jianqun Xu [port from vendor tree merging all fixes] Reviewed-by: Linus Walleij Signed-off-by: Sebastian Reichel --- .../boot/dts/rockchip/rk3588-pinctrl.dtsi | 516 +++ .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++ 2 files changed, 3919 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/= boot/dts/rockchip/rk3588-pinctrl.dtsi new file mode 100644 index 000000000000..244c66faa161 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + clk32k { + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins =3D + /* clk32k_out1 */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins =3D + /* eth0_refclko_25m */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + }; + + fspi { + /omit-if-no-ref/ + fspim1_pins: fspim1-pins { + rockchip,pins =3D + /* fspi_clk_m1 */ + <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m1 */ + <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m1 */ + <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m1 */ + <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m1 */ + <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m1 */ + <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim1_cs1: fspim1-cs1 { + rockchip,pins =3D + /* fspi_cs1n_m1 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins =3D + /* gmac0_mdc */ + <4 RK_PC4 1 &pcfg_pull_none>, + /* gmac0_mdio */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins =3D + /* gmac0_mclkinout */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins =3D + /* gmac0_rxd0 */ + <2 RK_PC1 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PC2 1 &pcfg_pull_none>, + /* gmac0_rxdv_crs */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins =3D + /* gmac0_txd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_txd1 */ + <2 RK_PB7 1 &pcfg_pull_none>, + /* gmac0_txen */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins =3D + /* gmac0_rxclk */ + <2 RK_PB0 1 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins =3D + /* gmac0_rxd2 */ + <2 RK_PA6 1 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA7 1 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PB1 1 &pcfg_pull_none>, + /* gmac0_txd3 */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppsclk: gmac0-ppsclk { + rockchip,pins =3D + /* gmac0_ppsclk */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppstring: gmac0-ppstring { + rockchip,pins =3D + /* gmac0_ppstring */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ptp_refclk: gmac0-ptp-refclk { + rockchip,pins =3D + /* gmac0_ptp_refclk */ + <2 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_txer: gmac0-txer { + rockchip,pins =3D + /* gmac0_txer */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_tx1_cec: hdmim0-tx1-cec { + rockchip,pins =3D + /* hdmim0_tx1_cec */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_scl: hdmim0-tx1-scl { + rockchip,pins =3D + /* hdmim0_tx1_scl */ + <2 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_sda: hdmim0-tx1-sda { + rockchip,pins =3D + /* hdmim0_tx1_sda */ + <2 RK_PB4 4 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins =3D + /* i2c0_scl_m1 */ + <4 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins =3D + /* i2c2_scl_m1 */ + <2 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <2 RK_PC0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m3_xfer: i2c3m3-xfer { + rockchip,pins =3D + /* i2c3_scl_m3 */ + <2 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m3 */ + <2 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins =3D + /* i2c4_scl_m1 */ + <2 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <2 RK_PB4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m4_xfer: i2c5m4-xfer { + rockchip,pins =3D + /* i2c5_scl_m4 */ + <2 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m4 */ + <2 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m2_xfer: i2c6m2-xfer { + rockchip,pins =3D + /* i2c6_scl_m2 */ + <2 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m2 */ + <2 RK_PC2 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m1_xfer: i2c7m1-xfer { + rockchip,pins =3D + /* i2c7_scl_m1 */ + <4 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m1 */ + <4 RK_PC4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m1_xfer: i2c8m1-xfer { + rockchip,pins =3D + /* i2c8_scl_m1 */ + <2 RK_PB0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m1 */ + <2 RK_PB1 9 &pcfg_pull_none_smt>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins =3D + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins =3D + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins =3D + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins =3D + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins =3D + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m2_pins: pwm2m2-pins { + rockchip,pins =3D + /* pwm2_m2 */ + <4 RK_PC2 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins =3D + /* pwm4_m1 */ + <4 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m2_pins: pwm5m2-pins { + rockchip,pins =3D + /* pwm5_m2 */ + <4 RK_PC4 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins =3D + /* pwm6_m2 */ + <4 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m3_pins: pwm7m3-pins { + rockchip,pins =3D + /* pwm7_ir_m3 */ + <4 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom0_pins: sdiom0-pins { + rockchip,pins =3D + /* sdio_clk_m0 */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* sdio_cmd_m0 */ + <2 RK_PB2 2 &pcfg_pull_none>, + /* sdio_d0_m0 */ + <2 RK_PA6 2 &pcfg_pull_none>, + /* sdio_d1_m0 */ + <2 RK_PA7 2 &pcfg_pull_none>, + /* sdio_d2_m0 */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* sdio_d3_m0 */ + <2 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins =3D + /* spi1_clk_m0 */ + <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m0 */ + <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m0 */ + <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins =3D + /* spi1_cs0_m0 */ + <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins =3D + /* spi1_cs1_m0 */ + <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins =3D + /* spi3_clk_m0 */ + <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m0 */ + <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m0 */ + <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins =3D + /* spi3_cs0_m0 */ + <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins =3D + /* spi3_cs1_m0 */ + <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins =3D + /* uart1_rx_m0 */ + <2 RK_PB6 10 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <2 RK_PB7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins =3D + /* uart1m0_ctsn */ + <2 RK_PC1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins =3D + /* uart1m0_rtsn */ + <2 RK_PC0 10 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins =3D + /* uart6_rx_m0 */ + <2 RK_PA6 10 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <2 RK_PA7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins =3D + /* uart6m0_ctsn */ + <2 RK_PB1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins =3D + /* uart6m0_rtsn */ + <2 RK_PB0 10 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins =3D + /* uart7_rx_m0 */ + <2 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <2 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins =3D + /* uart7m0_ctsn */ + <4 RK_PC6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins =3D + /* uart7m0_rtsn */ + <4 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins =3D + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins =3D + /* uart9m0_ctsn */ + <4 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins =3D + /* uart9m0_rtsn */ + <4 RK_PC4 10 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64= /boot/dts/rockchip/rk3588s-pinctrl.dtsi new file mode 100644 index 000000000000..48181671eacb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi @@ -0,0 +1,3403 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + auddsm { + /omit-if-no-ref/ + auddsm_pins: auddsm-pins { + rockchip,pins =3D + /* auddsm_ln */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* auddsm_lp */ + <3 RK_PA2 4 &pcfg_pull_none>, + /* auddsm_rn */ + <3 RK_PA3 4 &pcfg_pull_none>, + /* auddsm_rp */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins =3D + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <4 RK_PB7 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <4 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins =3D + /* can0_rx_m0 */ + <0 RK_PC0 11 &pcfg_pull_none>, + /* can0_tx_m0 */ + <0 RK_PB7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins =3D + /* can0_rx_m1 */ + <4 RK_PD5 9 &pcfg_pull_none>, + /* can0_tx_m1 */ + <4 RK_PD4 9 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins =3D + /* can1_rx_m0 */ + <3 RK_PB5 9 &pcfg_pull_none>, + /* can1_tx_m0 */ + <3 RK_PB6 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins =3D + /* can1_rx_m1 */ + <4 RK_PB2 12 &pcfg_pull_none>, + /* can1_tx_m1 */ + <4 RK_PB3 12 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins =3D + /* can2_rx_m0 */ + <3 RK_PC4 9 &pcfg_pull_none>, + /* can2_tx_m0 */ + <3 RK_PC5 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins =3D + /* can2_rx_m1 */ + <0 RK_PD4 10 &pcfg_pull_none>, + /* can2_tx_m1 */ + <0 RK_PD5 10 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins =3D + /* cif_clkout */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins =3D + /* cif_clkin */ + <4 RK_PB0 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB2 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins =3D + /* cif_d8 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* cif_d10 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d11 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d12 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d13 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d14 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d15 */ + <3 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins =3D + /* cif_d0 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d1 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d2 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d3 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d4 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d5 */ + <4 RK_PA5 1 &pcfg_pull_none>, + /* cif_d6 */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* cif_d7 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins =3D + /* clk32k_in */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins =3D + /* clk32k_out0 */ + <0 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins =3D + /* cpu_big0_avs */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* cpu_big1_avs */ + <0 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + ddrphych0 { + /omit-if-no-ref/ + ddrphych0_pins: ddrphych0-pins { + rockchip,pins =3D + /* ddrphych0_dtb0 */ + <4 RK_PA0 7 &pcfg_pull_none>, + /* ddrphych0_dtb1 */ + <4 RK_PA1 7 &pcfg_pull_none>, + /* ddrphych0_dtb2 */ + <4 RK_PA2 7 &pcfg_pull_none>, + /* ddrphych0_dtb3 */ + <4 RK_PA3 7 &pcfg_pull_none>; + }; + }; + + ddrphych1 { + /omit-if-no-ref/ + ddrphych1_pins: ddrphych1-pins { + rockchip,pins =3D + /* ddrphych1_dtb0 */ + <4 RK_PA4 7 &pcfg_pull_none>, + /* ddrphych1_dtb1 */ + <4 RK_PA5 7 &pcfg_pull_none>, + /* ddrphych1_dtb2 */ + <4 RK_PA6 7 &pcfg_pull_none>, + /* ddrphych1_dtb3 */ + <4 RK_PA7 7 &pcfg_pull_none>; + }; + }; + + ddrphych2 { + /omit-if-no-ref/ + ddrphych2_pins: ddrphych2-pins { + rockchip,pins =3D + /* ddrphych2_dtb0 */ + <4 RK_PB0 7 &pcfg_pull_none>, + /* ddrphych2_dtb1 */ + <4 RK_PB1 7 &pcfg_pull_none>, + /* ddrphych2_dtb2 */ + <4 RK_PB2 7 &pcfg_pull_none>, + /* ddrphych2_dtb3 */ + <4 RK_PB3 7 &pcfg_pull_none>; + }; + }; + + ddrphych3 { + /omit-if-no-ref/ + ddrphych3_pins: ddrphych3-pins { + rockchip,pins =3D + /* ddrphych3_dtb0 */ + <4 RK_PB4 7 &pcfg_pull_none>, + /* ddrphych3_dtb1 */ + <4 RK_PB5 7 &pcfg_pull_none>, + /* ddrphych3_dtb2 */ + <4 RK_PB6 7 &pcfg_pull_none>, + /* ddrphych3_dtb3 */ + <4 RK_PB7 7 &pcfg_pull_none>; + }; + }; + + dp0 { + /omit-if-no-ref/ + dp0m0_pins: dp0m0-pins { + rockchip,pins =3D + /* dp0_hpdin_m0 */ + <4 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m1_pins: dp0m1-pins { + rockchip,pins =3D + /* dp0_hpdin_m1 */ + <0 RK_PC4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m2_pins: dp0m2-pins { + rockchip,pins =3D + /* dp0_hpdin_m2 */ + <1 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + dp1 { + /omit-if-no-ref/ + dp1m0_pins: dp1m0-pins { + rockchip,pins =3D + /* dp1_hpdin_m0 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m1_pins: dp1m1-pins { + rockchip,pins =3D + /* dp1_hpdin_m1 */ + <0 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m2_pins: dp1m2-pins { + rockchip,pins =3D + /* dp1_hpdin_m2 */ + <1 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins =3D + /* emmc_rstn */ + <2 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins =3D + /* emmc_d0 */ + <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins =3D + /* emmc_clkout */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins =3D + /* emmc_cmd */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_data_strobe: emmc-data-strobe { + rockchip,pins =3D + /* emmc_data_strobe */ + <2 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1_pins: eth1-pins { + rockchip,pins =3D + /* eth1_refclko_25m */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspim0_pins: fspim0-pins { + rockchip,pins =3D + /* fspi_clk_m0 */ + <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m0 */ + <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m0 */ + <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m0 */ + <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m0 */ + <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m0 */ + <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim0_cs1: fspim0-cs1 { + rockchip,pins =3D + /* fspi_cs1n_m0 */ + <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_pins: fspim2-pins { + rockchip,pins =3D + /* fspi_clk_m2 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m2 */ + <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m2 */ + <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m2 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m2 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m2 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_cs1: fspim2-cs1 { + rockchip,pins =3D + /* fspi_cs1n_m2 */ + <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1_miim: gmac1-miim { + rockchip,pins =3D + /* gmac1_mdc */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* gmac1_mdio */ + <3 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_clkinout: gmac1-clkinout { + rockchip,pins =3D + /* gmac1_mclkinout */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rx_bus2: gmac1-rx-bus2 { + rockchip,pins =3D + /* gmac1_rxd0 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* gmac1_rxd1 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* gmac1_rxdv_crs */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_tx_bus2: gmac1-tx-bus2 { + rockchip,pins =3D + /* gmac1_txd0 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* gmac1_txd1 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* gmac1_txen */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_clk: gmac1-rgmii-clk { + rockchip,pins =3D + /* gmac1_rxclk */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* gmac1_txclk */ + <3 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_bus: gmac1-rgmii-bus { + rockchip,pins =3D + /* gmac1_rxd2 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* gmac1_rxd3 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* gmac1_txd2 */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* gmac1_txd3 */ + <3 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppsclk: gmac1-ppsclk { + rockchip,pins =3D + /* gmac1_ppsclk */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppstrig: gmac1-ppstrig { + rockchip,pins =3D + /* gmac1_ppstrig */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { + rockchip,pins =3D + /* gmac1_ptp_ref_clk */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_txer: gmac1-txer { + rockchip,pins =3D + /* gmac1_txer */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins =3D + /* gpu_avs */ + <0 RK_PC5 2 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_rx_cec: hdmim0-rx-cec { + rockchip,pins =3D + /* hdmim0_rx_cec */ + <4 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_hpdin: hdmim0-rx-hpdin { + rockchip,pins =3D + /* hdmim0_rx_hpdin */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_scl: hdmim0-rx-scl { + rockchip,pins =3D + /* hdmim0_rx_scl */ + <0 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_sda: hdmim0-rx-sda { + rockchip,pins =3D + /* hdmim0_rx_sda */ + <0 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_cec: hdmim0-tx0-cec { + rockchip,pins =3D + /* hdmim0_tx0_cec */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_hpd: hdmim0-tx0-hpd { + rockchip,pins =3D + /* hdmim0_tx0_hpd */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_scl: hdmim0-tx0-scl { + rockchip,pins =3D + /* hdmim0_tx0_scl */ + <4 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_sda: hdmim0-tx0-sda { + rockchip,pins =3D + /* hdmim0_tx0_sda */ + <4 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_hpd: hdmim0-tx1-hpd { + rockchip,pins =3D + /* hdmim0_tx1_hpd */ + <1 RK_PA6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmim1_rx_cec: hdmim1-rx-cec { + rockchip,pins =3D + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_hpdin: hdmim1-rx-hpdin { + rockchip,pins =3D + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_scl: hdmim1-rx-scl { + rockchip,pins =3D + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_sda: hdmim1-rx-sda { + rockchip,pins =3D + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_cec: hdmim1-tx0-cec { + rockchip,pins =3D + /* hdmim1_tx0_cec */ + <0 RK_PD1 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_hpd: hdmim1-tx0-hpd { + rockchip,pins =3D + /* hdmim1_tx0_hpd */ + <3 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_scl: hdmim1-tx0-scl { + rockchip,pins =3D + /* hdmim1_tx0_scl */ + <0 RK_PD5 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_sda: hdmim1-tx0-sda { + rockchip,pins =3D + /* hdmim1_tx0_sda */ + <0 RK_PD4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_cec: hdmim1-tx1-cec { + rockchip,pins =3D + /* hdmim1_tx1_cec */ + <0 RK_PD2 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_hpd: hdmim1-tx1-hpd { + rockchip,pins =3D + /* hdmim1_tx1_hpd */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_scl: hdmim1-tx1-scl { + rockchip,pins =3D + /* hdmim1_tx1_scl */ + <3 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_sda: hdmim1-tx1-sda { + rockchip,pins =3D + /* hdmim1_tx1_sda */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmim2_rx_cec: hdmim2-rx-cec { + rockchip,pins =3D + /* hdmim2_rx_cec */ + <1 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_hpdin: hdmim2-rx-hpdin { + rockchip,pins =3D + /* hdmim2_rx_hpdin */ + <1 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_scl: hdmim2-rx-scl { + rockchip,pins =3D + /* hdmim2_rx_scl */ + <1 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_sda: hdmim2-rx-sda { + rockchip,pins =3D + /* hdmim2_rx_sda */ + <1 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_scl: hdmim2-tx0-scl { + rockchip,pins =3D + /* hdmim2_tx0_scl */ + <3 RK_PC7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_sda: hdmim2-tx0-sda { + rockchip,pins =3D + /* hdmim2_tx0_sda */ + <3 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_cec: hdmim2-tx1-cec { + rockchip,pins =3D + /* hdmim2_tx1_cec */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_scl: hdmim2-tx1-scl { + rockchip,pins =3D + /* hdmim2_tx1_scl */ + <1 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_sda: hdmim2-tx1-sda { + rockchip,pins =3D + /* hdmim2_tx1_sda */ + <1 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug0: hdmi-debug0 { + rockchip,pins =3D + /* hdmi_debug0 */ + <1 RK_PA7 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug1: hdmi-debug1 { + rockchip,pins =3D + /* hdmi_debug1 */ + <1 RK_PB0 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug2: hdmi-debug2 { + rockchip,pins =3D + /* hdmi_debug2 */ + <1 RK_PB1 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug3: hdmi-debug3 { + rockchip,pins =3D + /* hdmi_debug3 */ + <1 RK_PB2 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug4: hdmi-debug4 { + rockchip,pins =3D + /* hdmi_debug4 */ + <1 RK_PB3 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug5: hdmi-debug5 { + rockchip,pins =3D + /* hdmi_debug5 */ + <1 RK_PB4 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug6: hdmi-debug6 { + rockchip,pins =3D + /* hdmi_debug6 */ + <1 RK_PA0 7 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins =3D + /* i2c0_scl_m0 */ + <0 RK_PB3 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <0 RK_PA6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins =3D + /* i2c0_scl_m2 */ + <0 RK_PD1 3 &pcfg_pull_none_smt>, + /* i2c0_sda_m2 */ + <0 RK_PD2 3 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins =3D + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins =3D + /* i2c1_scl_m1 */ + <0 RK_PB0 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <0 RK_PB1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m2_xfer: i2c1m2-xfer { + rockchip,pins =3D + /* i2c1_scl_m2 */ + <0 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m2 */ + <0 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m3_xfer: i2c1m3-xfer { + rockchip,pins =3D + /* i2c1_scl_m3 */ + <2 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m3 */ + <2 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m4_xfer: i2c1m4-xfer { + rockchip,pins =3D + /* i2c1_scl_m4 */ + <1 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m4 */ + <1 RK_PD3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins =3D + /* i2c2_scl_m0 */ + <0 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m2_xfer: i2c2m2-xfer { + rockchip,pins =3D + /* i2c2_scl_m2 */ + <2 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m2 */ + <2 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m3_xfer: i2c2m3-xfer { + rockchip,pins =3D + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m4_xfer: i2c2m4-xfer { + rockchip,pins =3D + /* i2c2_scl_m4 */ + <1 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m4 */ + <1 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins =3D + /* i2c3_scl_m0 */ + <1 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins =3D + /* i2c3_scl_m1 */ + <3 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins =3D + /* i2c3_scl_m2 */ + <4 RK_PA4 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m2 */ + <4 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m4_xfer: i2c3m4-xfer { + rockchip,pins =3D + /* i2c3_scl_m4 */ + <4 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m4 */ + <4 RK_PD1 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins =3D + /* i2c4_scl_m0 */ + <3 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m2_xfer: i2c4m2-xfer { + rockchip,pins =3D + /* i2c4_scl_m2 */ + <0 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m2 */ + <0 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m3_xfer: i2c4m3-xfer { + rockchip,pins =3D + /* i2c4_scl_m3 */ + <1 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m3 */ + <1 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m4_xfer: i2c4m4-xfer { + rockchip,pins =3D + /* i2c4_scl_m4 */ + <1 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m4 */ + <1 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins =3D + /* i2c5_scl_m0 */ + <3 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PD0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins =3D + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m2_xfer: i2c5m2-xfer { + rockchip,pins =3D + /* i2c5_scl_m2 */ + <4 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m2 */ + <4 RK_PA7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m3_xfer: i2c5m3-xfer { + rockchip,pins =3D + /* i2c5_scl_m3 */ + <1 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m3 */ + <1 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins =3D + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins =3D + /* i2c6_scl_m1 */ + <1 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PC2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m3_xfer: i2c6m3-xfer { + rockchip,pins =3D + /* i2c6_scl_m3 */ + <4 RK_PB1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m3 */ + <4 RK_PB0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m4_xfer: i2c6m4-xfer { + rockchip,pins =3D + /* i2c6_scl_m4 */ + <3 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m4 */ + <3 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m0_xfer: i2c7m0-xfer { + rockchip,pins =3D + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m2_xfer: i2c7m2-xfer { + rockchip,pins =3D + /* i2c7_scl_m2 */ + <3 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m2 */ + <3 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m3_xfer: i2c7m3-xfer { + rockchip,pins =3D + /* i2c7_scl_m3 */ + <4 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m3 */ + <4 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m0_xfer: i2c8m0-xfer { + rockchip,pins =3D + /* i2c8_scl_m0 */ + <4 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m0 */ + <4 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m2_xfer: i2c8m2-xfer { + rockchip,pins =3D + /* i2c8_scl_m2 */ + <1 RK_PD6 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m2 */ + <1 RK_PD7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m3_xfer: i2c8m3-xfer { + rockchip,pins =3D + /* i2c8_scl_m3 */ + <4 RK_PC0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m3 */ + <4 RK_PC1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m4_xfer: i2c8m4-xfer { + rockchip,pins =3D + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0_lrck: i2s0-lrck { + rockchip,pins =3D + /* i2s0_lrck */ + <1 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_mclk: i2s0-mclk { + rockchip,pins =3D + /* i2s0_mclk */ + <1 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sclk: i2s0-sclk { + rockchip,pins =3D + /* i2s0_sclk */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi0: i2s0-sdi0 { + rockchip,pins =3D + /* i2s0_sdi0 */ + <1 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi1: i2s0-sdi1 { + rockchip,pins =3D + /* i2s0_sdi1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi2: i2s0-sdi2 { + rockchip,pins =3D + /* i2s0_sdi2 */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi3: i2s0-sdi3 { + rockchip,pins =3D + /* i2s0_sdi3 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo0: i2s0-sdo0 { + rockchip,pins =3D + /* i2s0_sdo0 */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo1: i2s0-sdo1 { + rockchip,pins =3D + /* i2s0_sdo1 */ + <1 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo2: i2s0-sdo2 { + rockchip,pins =3D + /* i2s0_sdo2 */ + <1 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo3: i2s0-sdo3 { + rockchip,pins =3D + /* i2s0_sdo3 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins =3D + /* i2s1m0_lrck */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins =3D + /* i2s1m0_mclk */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins =3D + /* i2s1m0_sclk */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins =3D + /* i2s1m0_sdi0 */ + <4 RK_PA5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins =3D + /* i2s1m0_sdi1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins =3D + /* i2s1m0_sdi2 */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins =3D + /* i2s1m0_sdi3 */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins =3D + /* i2s1m0_sdo0 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins =3D + /* i2s1m0_sdo1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins =3D + /* i2s1m0_sdo2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins =3D + /* i2s1m0_sdo3 */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins =3D + /* i2s1m1_lrck */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins =3D + /* i2s1m1_mclk */ + <0 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins =3D + /* i2s1m1_sclk */ + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins =3D + /* i2s1m1_sdi0 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins =3D + /* i2s1m1_sdi1 */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins =3D + /* i2s1m1_sdi2 */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins =3D + /* i2s1m1_sdi3 */ + <0 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins =3D + /* i2s1m1_sdo0 */ + <0 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins =3D + /* i2s1m1_sdo1 */ + <0 RK_PD2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins =3D + /* i2s1m1_sdo2 */ + <0 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins =3D + /* i2s1m1_sdo3 */ + <0 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins =3D + /* i2s2m1_lrck */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins =3D + /* i2s2m1_mclk */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins =3D + /* i2s2m1_sclk */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins =3D + /* i2s2m1_sdi */ + <3 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins =3D + /* i2s2m1_sdo */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3_lrck: i2s3-lrck { + rockchip,pins =3D + /* i2s3_lrck */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_mclk: i2s3-mclk { + rockchip,pins =3D + /* i2s3_mclk */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sclk: i2s3-sclk { + rockchip,pins =3D + /* i2s3_sclk */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdi: i2s3-sdi { + rockchip,pins =3D + /* i2s3_sdi */ + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdo: i2s3-sdo { + rockchip,pins =3D + /* i2s3_sdo */ + <3 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins =3D + /* jtag_tck_m0 */ + <4 RK_PD2 5 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <4 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins =3D + /* jtag_tck_m1 */ + <4 RK_PD0 5 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <4 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm2_pins: jtagm2-pins { + rockchip,pins =3D + /* jtag_tck_m2 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + litcpu { + /omit-if-no-ref/ + litcpu_pins: litcpu-pins { + rockchip,pins =3D + /* litcpu_avs */ + <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcum0_pins: mcum0-pins { + rockchip,pins =3D + /* mcu_jtag_tck_m0 */ + <4 RK_PD4 5 &pcfg_pull_none>, + /* mcu_jtag_tms_m0 */ + <4 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mcum1_pins: mcum1-pins { + rockchip,pins =3D + /* mcu_jtag_tck_m1 */ + <3 RK_PD4 6 &pcfg_pull_none>, + /* mcu_jtag_tms_m1 */ + <3 RK_PD5 6 &pcfg_pull_none>; + }; + }; + + mipi { + /omit-if-no-ref/ + mipim0_camera0_clk: mipim0-camera0-clk { + rockchip,pins =3D + /* mipim0_camera0_clk */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera1_clk: mipim0-camera1-clk { + rockchip,pins =3D + /* mipim0_camera1_clk */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera2_clk: mipim0-camera2-clk { + rockchip,pins =3D + /* mipim0_camera2_clk */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera3_clk: mipim0-camera3-clk { + rockchip,pins =3D + /* mipim0_camera3_clk */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera4_clk: mipim0-camera4-clk { + rockchip,pins =3D + /* mipim0_camera4_clk */ + <1 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera0_clk: mipim1-camera0-clk { + rockchip,pins =3D + /* mipim1_camera0_clk */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera1_clk: mipim1-camera1-clk { + rockchip,pins =3D + /* mipim1_camera1_clk */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera2_clk: mipim1-camera2-clk { + rockchip,pins =3D + /* mipim1_camera2_clk */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera3_clk: mipim1-camera3-clk { + rockchip,pins =3D + /* mipim1_camera3_clk */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera4_clk: mipim1-camera4-clk { + rockchip,pins =3D + /* mipim1_camera4_clk */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te0: mipi-te0 { + rockchip,pins =3D + /* mipi_te0 */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te1: mipi-te1 { + rockchip,pins =3D + /* mipi_te1 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins =3D + /* npu_avs */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + pcie20x1 { + /omit-if-no-ref/ + pcie20x1m0_pins: pcie20x1m0-pins { + rockchip,pins =3D + /* pcie20x1_2_clkreqn_m0 */ + <3 RK_PC7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m0 */ + <3 RK_PD1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m0 */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_pins: pcie20x1m1-pins { + rockchip,pins =3D + /* pcie20x1_2_clkreqn_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m1 */ + <4 RK_PC1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m1 */ + <4 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { + rockchip,pins =3D + /* pcie20x1_2_button_rstn */ + <4 RK_PB3 4 &pcfg_pull_none>; + }; + }; + + pcie30phy { + /omit-if-no-ref/ + pcie30phy_pins: pcie30phy-pins { + rockchip,pins =3D + /* pcie30phy_dtb0 */ + <1 RK_PC4 4 &pcfg_pull_none>, + /* pcie30phy_dtb1 */ + <1 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins =3D + /* pcie30x1_0_clkreqn_m0 */ + <0 RK_PC0 12 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m0 */ + <0 RK_PC5 12 &pcfg_pull_none>, + /* pcie30x1_0_waken_m0 */ + <0 RK_PC4 12 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m0 */ + <0 RK_PB5 12 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m0 */ + <0 RK_PB7 12 &pcfg_pull_none>, + /* pcie30x1_1_waken_m0 */ + <0 RK_PB6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins =3D + /* pcie30x1_0_clkreqn_m1 */ + <4 RK_PA3 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m1 */ + <4 RK_PA4 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m1 */ + <4 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m1 */ + <4 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins =3D + /* pcie30x1_0_clkreqn_m2 */ + <1 RK_PB5 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m2 */ + <1 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m2 */ + <1 RK_PB3 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m2 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m2 */ + <1 RK_PA7 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m2 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { + rockchip,pins =3D + /* pcie30x1_0_button_rstn */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { + rockchip,pins =3D + /* pcie30x1_1_button_rstn */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins =3D + /* pcie30x2_clkreqn_m0 */ + <0 RK_PD1 12 &pcfg_pull_none>, + /* pcie30x2_perstn_m0 */ + <0 RK_PD4 12 &pcfg_pull_none>, + /* pcie30x2_waken_m0 */ + <0 RK_PD2 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins =3D + /* pcie30x2_clkreqn_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x2_waken_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins =3D + /* pcie30x2_clkreqn_m2 */ + <3 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m2 */ + <3 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_waken_m2 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_pins: pcie30x2m3-pins { + rockchip,pins =3D + /* pcie30x2_clkreqn_m3 */ + <1 RK_PD7 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m3 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* pcie30x2_waken_m3 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_button_rstn: pcie30x2-button-rstn { + rockchip,pins =3D + /* pcie30x2_button_rstn */ + <3 RK_PC1 4 &pcfg_pull_none>; + }; + }; + + pcie30x4 { + /omit-if-no-ref/ + pcie30x4m0_pins: pcie30x4m0-pins { + rockchip,pins =3D + /* pcie30x4_clkreqn_m0 */ + <0 RK_PC6 12 &pcfg_pull_none>, + /* pcie30x4_perstn_m0 */ + <0 RK_PD0 12 &pcfg_pull_none>, + /* pcie30x4_waken_m0 */ + <0 RK_PC7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_pins: pcie30x4m1-pins { + rockchip,pins =3D + /* pcie30x4_clkreqn_m1 */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m1 */ + <4 RK_PB6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_pins: pcie30x4m2-pins { + rockchip,pins =3D + /* pcie30x4_clkreqn_m2 */ + <3 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m2 */ + <3 RK_PC6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m2 */ + <3 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_pins: pcie30x4m3-pins { + rockchip,pins =3D + /* pcie30x4_clkreqn_m3 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m3 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie30x4_waken_m3 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4_button_rstn: pcie30x4-button-rstn { + rockchip,pins =3D + /* pcie30x4_button_rstn */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pdm0 { + /omit-if-no-ref/ + pdm0m0_clk: pdm0m0-clk { + rockchip,pins =3D + /* pdm0_clk0_m0 */ + <1 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_clk1: pdm0m0-clk1 { + rockchip,pins =3D + /* pdm0m0_clk1 */ + <1 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi0: pdm0m0-sdi0 { + rockchip,pins =3D + /* pdm0m0_sdi0 */ + <1 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi1: pdm0m0-sdi1 { + rockchip,pins =3D + /* pdm0m0_sdi1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi2: pdm0m0-sdi2 { + rockchip,pins =3D + /* pdm0m0_sdi2 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi3: pdm0m0-sdi3 { + rockchip,pins =3D + /* pdm0m0_sdi3 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm0m1_clk: pdm0m1-clk { + rockchip,pins =3D + /* pdm0_clk0_m1 */ + <0 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_clk1: pdm0m1-clk1 { + rockchip,pins =3D + /* pdm0m1_clk1 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi0: pdm0m1-sdi0 { + rockchip,pins =3D + /* pdm0m1_sdi0 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi1: pdm0m1-sdi1 { + rockchip,pins =3D + /* pdm0m1_sdi1 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi2: pdm0m1-sdi2 { + rockchip,pins =3D + /* pdm0m1_sdi2 */ + <0 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi3: pdm0m1-sdi3 { + rockchip,pins =3D + /* pdm0m1_sdi3 */ + <0 RK_PD6 2 &pcfg_pull_none>; + }; + }; + + pdm1 { + /omit-if-no-ref/ + pdm1m0_clk: pdm1m0-clk { + rockchip,pins =3D + /* pdm1_clk0_m0 */ + <4 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_clk1: pdm1m0-clk1 { + rockchip,pins =3D + /* pdm1m0_clk1 */ + <4 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi0: pdm1m0-sdi0 { + rockchip,pins =3D + /* pdm1m0_sdi0 */ + <4 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi1: pdm1m0-sdi1 { + rockchip,pins =3D + /* pdm1m0_sdi1 */ + <4 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi2: pdm1m0-sdi2 { + rockchip,pins =3D + /* pdm1m0_sdi2 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi3: pdm1m0-sdi3 { + rockchip,pins =3D + /* pdm1m0_sdi3 */ + <4 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm1m1_clk: pdm1m1-clk { + rockchip,pins =3D + /* pdm1_clk0_m1 */ + <1 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_clk1: pdm1m1-clk1 { + rockchip,pins =3D + /* pdm1m1_clk1 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi0: pdm1m1-sdi0 { + rockchip,pins =3D + /* pdm1m1_sdi0 */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi1: pdm1m1-sdi1 { + rockchip,pins =3D + /* pdm1m1_sdi1 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi2: pdm1m1-sdi2 { + rockchip,pins =3D + /* pdm1m1_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi3: pdm1m1-sdi3 { + rockchip,pins =3D + /* pdm1m1_sdi3 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins =3D + /* pmic_int_l */ + <0 RK_PA7 0 &pcfg_pull_up>, + /* pmic_sleep1 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pmic_sleep2 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pmic_sleep3 */ + <0 RK_PC1 1 &pcfg_pull_none>, + /* pmic_sleep4 */ + <0 RK_PC2 1 &pcfg_pull_none>, + /* pmic_sleep5 */ + <0 RK_PC3 1 &pcfg_pull_none>, + /* pmic_sleep6 */ + <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins =3D + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins =3D + /* pwm0_m0 */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins =3D + /* pwm0_m1 */ + <1 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m2_pins: pwm0m2-pins { + rockchip,pins =3D + /* pwm0_m2 */ + <1 RK_PA2 11 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins =3D + /* pwm1_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins =3D + /* pwm1_m1 */ + <1 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m2_pins: pwm1m2-pins { + rockchip,pins =3D + /* pwm1_m2 */ + <1 RK_PA3 11 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins =3D + /* pwm2_m0 */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins =3D + /* pwm2_m1 */ + <3 RK_PB1 11 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins =3D + /* pwm3_ir_m0 */ + <0 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins =3D + /* pwm3_ir_m1 */ + <3 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m2_pins: pwm3m2-pins { + rockchip,pins =3D + /* pwm3_ir_m2 */ + <1 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m3_pins: pwm3m3-pins { + rockchip,pins =3D + /* pwm3_ir_m3 */ + <1 RK_PA7 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins =3D + /* pwm4_m0 */ + <0 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins =3D + /* pwm5_m0 */ + <0 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins =3D + /* pwm5_m1 */ + <0 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins =3D + /* pwm6_m0 */ + <0 RK_PC7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins =3D + /* pwm6_m1 */ + <4 RK_PC1 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins =3D + /* pwm7_ir_m0 */ + <0 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins =3D + /* pwm7_ir_m1 */ + <4 RK_PD4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m2_pins: pwm7m2-pins { + rockchip,pins =3D + /* pwm7_ir_m2 */ + <1 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins =3D + /* pwm8_m0 */ + <3 RK_PA7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins =3D + /* pwm8_m1 */ + <4 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m2_pins: pwm8m2-pins { + rockchip,pins =3D + /* pwm8_m2 */ + <3 RK_PD0 11 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins =3D + /* pwm9_m0 */ + <3 RK_PB0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins =3D + /* pwm9_m1 */ + <4 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m2_pins: pwm9m2-pins { + rockchip,pins =3D + /* pwm9_m2 */ + <3 RK_PD1 11 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins =3D + /* pwm10_m0 */ + <3 RK_PA0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins =3D + /* pwm10_m1 */ + <4 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m2_pins: pwm10m2-pins { + rockchip,pins =3D + /* pwm10_m2 */ + <3 RK_PD3 11 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins =3D + /* pwm11_ir_m0 */ + <3 RK_PA1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins =3D + /* pwm11_ir_m1 */ + <4 RK_PB4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m2_pins: pwm11m2-pins { + rockchip,pins =3D + /* pwm11_ir_m2 */ + <1 RK_PC4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m3_pins: pwm11m3-pins { + rockchip,pins =3D + /* pwm11_ir_m3 */ + <3 RK_PD5 11 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins =3D + /* pwm12_m0 */ + <3 RK_PB5 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins =3D + /* pwm12_m1 */ + <4 RK_PB5 11 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins =3D + /* pwm13_m0 */ + <3 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins =3D + /* pwm13_m1 */ + <4 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m2_pins: pwm13m2-pins { + rockchip,pins =3D + /* pwm13_m2 */ + <1 RK_PB7 11 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins =3D + /* pwm14_m0 */ + <3 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins =3D + /* pwm14_m1 */ + <4 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m2_pins: pwm14m2-pins { + rockchip,pins =3D + /* pwm14_m2 */ + <1 RK_PD6 11 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins =3D + /* pwm15_ir_m0 */ + <3 RK_PC3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins =3D + /* pwm15_ir_m1 */ + <4 RK_PB3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m2_pins: pwm15m2-pins { + rockchip,pins =3D + /* pwm15_ir_m2 */ + <1 RK_PC6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m3_pins: pwm15m3-pins { + rockchip,pins =3D + /* pwm15_ir_m3 */ + <1 RK_PD7 11 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins =3D + /* refclk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins =3D + /* sata_cp_pod */ + <0 RK_PC6 13 &pcfg_pull_none>, + /* sata_cpdet */ + <0 RK_PD4 13 &pcfg_pull_none>, + /* sata_mp_switch */ + <0 RK_PD5 13 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0m0_pins: sata0m0-pins { + rockchip,pins =3D + /* sata0_act_led_m0 */ + <4 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata0m1_pins: sata0m1-pins { + rockchip,pins =3D + /* sata0_act_led_m1 */ + <1 RK_PB3 6 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1m0_pins: sata1m0-pins { + rockchip,pins =3D + /* sata1_act_led_m0 */ + <4 RK_PB5 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata1m1_pins: sata1m1-pins { + rockchip,pins =3D + /* sata1_act_led_m1 */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2m0_pins: sata2m0-pins { + rockchip,pins =3D + /* sata2_act_led_m0 */ + <4 RK_PB1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata2m1_pins: sata2m1-pins { + rockchip,pins =3D + /* sata2_act_led_m1 */ + <1 RK_PB7 6 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom1_pins: sdiom1-pins { + rockchip,pins =3D + /* sdio_clk_m1 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* sdio_cmd_m1 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* sdio_d0_m1 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* sdio_d1_m1 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* sdio_d2_m1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* sdio_d3_m1 */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins =3D + /* sdmmc_d0 */ + <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins =3D + /* sdmmc_clk */ + <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins =3D + /* sdmmc_cmd */ + <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins =3D + /* sdmmc_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins =3D + /* sdmmc_pwren */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + spdif0 { + /omit-if-no-ref/ + spdif0m0_tx: spdif0m0-tx { + rockchip,pins =3D + /* spdif0m0_tx */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif0m1_tx: spdif0m1-tx { + rockchip,pins =3D + /* spdif0m1_tx */ + <4 RK_PB4 6 &pcfg_pull_none>; + }; + }; + + spdif1 { + /omit-if-no-ref/ + spdif1m0_tx: spdif1m0-tx { + rockchip,pins =3D + /* spdif1m0_tx */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m1_tx: spdif1m1-tx { + rockchip,pins =3D + /* spdif1m1_tx */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m2_tx: spdif1m2-tx { + rockchip,pins =3D + /* spdif1m2_tx */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins =3D + /* spi0_clk_m0 */ + <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m0 */ + <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m0 */ + <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins =3D + /* spi0_cs0_m0 */ + <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins =3D + /* spi0_cs1_m0 */ + <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins =3D + /* spi0_clk_m1 */ + <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m1 */ + <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m1 */ + <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins =3D + /* spi0_cs0_m1 */ + <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins =3D + /* spi0_cs1_m1 */ + <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m2_pins: spi0m2-pins { + rockchip,pins =3D + /* spi0_clk_m2 */ + <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m2 */ + <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m2 */ + <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins =3D + /* spi0_cs0_m2 */ + <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m2_cs1: spi0m2-cs1 { + rockchip,pins =3D + /* spi0_cs1_m2 */ + <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m3_pins: spi0m3-pins { + rockchip,pins =3D + /* spi0_clk_m3 */ + <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m3 */ + <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m3 */ + <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m3_cs0: spi0m3-cs0 { + rockchip,pins =3D + /* spi0_cs0_m3 */ + <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m3_cs1: spi0m3-cs1 { + rockchip,pins =3D + /* spi0_cs1_m3 */ + <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins =3D + /* spi1_clk_m1 */ + <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m1 */ + <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m1 */ + <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins =3D + /* spi1_cs0_m1 */ + <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs1: spi1m1-cs1 { + rockchip,pins =3D + /* spi1_cs1_m1 */ + <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_pins: spi1m2-pins { + rockchip,pins =3D + /* spi1_clk_m2 */ + <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m2 */ + <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m2 */ + <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_cs0: spi1m2-cs0 { + rockchip,pins =3D + /* spi1_cs0_m2 */ + <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_cs1: spi1m2-cs1 { + rockchip,pins =3D + /* spi1_cs1_m2 */ + <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins =3D + /* spi2_clk_m0 */ + <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m0 */ + <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m0 */ + <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins =3D + /* spi2_cs0_m0 */ + <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins =3D + /* spi2_cs1_m0 */ + <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins =3D + /* spi2_clk_m1 */ + <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m1 */ + <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m1 */ + <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins =3D + /* spi2_cs0_m1 */ + <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins =3D + /* spi2_cs1_m1 */ + <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_pins: spi2m2-pins { + rockchip,pins =3D + /* spi2_clk_m2 */ + <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m2 */ + <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m2 */ + <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs0: spi2m2-cs0 { + rockchip,pins =3D + /* spi2_cs0_m2 */ + <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs1: spi2m2-cs1 { + rockchip,pins =3D + /* spi2_cs1_m2 */ + <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins =3D + /* spi3_clk_m1 */ + <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m1 */ + <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m1 */ + <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins =3D + /* spi3_cs0_m1 */ + <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins =3D + /* spi3_cs1_m1 */ + <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_pins: spi3m2-pins { + rockchip,pins =3D + /* spi3_clk_m2 */ + <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m2 */ + <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m2 */ + <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_cs0: spi3m2-cs0 { + rockchip,pins =3D + /* spi3_cs0_m2 */ + <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_cs1: spi3m2-cs1 { + rockchip,pins =3D + /* spi3_cs1_m2 */ + <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_pins: spi3m3-pins { + rockchip,pins =3D + /* spi3_clk_m3 */ + <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m3 */ + <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m3 */ + <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_cs0: spi3m3-cs0 { + rockchip,pins =3D + /* spi3_cs0_m3 */ + <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_cs1: spi3m3-cs1 { + rockchip,pins =3D + /* spi3_cs1_m3 */ + <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi4 { + /omit-if-no-ref/ + spi4m0_pins: spi4m0-pins { + rockchip,pins =3D + /* spi4_clk_m0 */ + <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m0 */ + <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m0 */ + <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m0_cs0: spi4m0-cs0 { + rockchip,pins =3D + /* spi4_cs0_m0 */ + <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m0_cs1: spi4m0-cs1 { + rockchip,pins =3D + /* spi4_cs1_m0 */ + <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_pins: spi4m1-pins { + rockchip,pins =3D + /* spi4_clk_m1 */ + <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m1 */ + <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m1 */ + <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_cs0: spi4m1-cs0 { + rockchip,pins =3D + /* spi4_cs0_m1 */ + <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_cs1: spi4m1-cs1 { + rockchip,pins =3D + /* spi4_cs1_m1 */ + <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m2_pins: spi4m2-pins { + rockchip,pins =3D + /* spi4_clk_m2 */ + <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m2 */ + <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m2 */ + <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m2_cs0: spi4m2-cs0 { + rockchip,pins =3D + /* spi4_cs0_m2 */ + <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins =3D + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut: tsadc-shut { + rockchip,pins =3D + /* tsadc_shut */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins =3D + /* tsadc_shut_org */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins =3D + /* uart0_rx_m0 */ + <0 RK_PC4 4 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins =3D + /* uart0_rx_m1 */ + <0 RK_PB0 4 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <0 RK_PB1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m2_xfer: uart0m2-xfer { + rockchip,pins =3D + /* uart0_rx_m2 */ + <4 RK_PA4 10 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <4 RK_PA3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins =3D + /* uart0_ctsn */ + <0 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins =3D + /* uart0_rtsn */ + <0 RK_PC6 4 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins =3D + /* uart1_rx_m1 */ + <1 RK_PB7 10 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PB6 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins =3D + /* uart1m1_ctsn */ + <1 RK_PD7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins =3D + /* uart1m1_rtsn */ + <1 RK_PD6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_xfer: uart1m2-xfer { + rockchip,pins =3D + /* uart1_rx_m2 */ + <0 RK_PD2 10 &pcfg_pull_up>, + /* uart1_tx_m2 */ + <0 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins =3D + /* uart1m2_ctsn */ + <0 RK_PD0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins =3D + /* uart1m2_rtsn */ + <0 RK_PC7 10 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins =3D + /* uart2_rx_m0 */ + <0 RK_PB6 10 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins =3D + /* uart2_rx_m1 */ + <4 RK_PD1 10 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <4 RK_PD0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m2_xfer: uart2m2-xfer { + rockchip,pins =3D + /* uart2_rx_m2 */ + <3 RK_PB2 10 &pcfg_pull_up>, + /* uart2_tx_m2 */ + <3 RK_PB1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2_ctsn: uart2-ctsn { + rockchip,pins =3D + /* uart2_ctsn */ + <3 RK_PB4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2_rtsn: uart2-rtsn { + rockchip,pins =3D + /* uart2_rtsn */ + <3 RK_PB3 10 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins =3D + /* uart3_rx_m0 */ + <1 RK_PC0 10 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <1 RK_PC1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins =3D + /* uart3_rx_m1 */ + <3 RK_PB6 10 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins =3D + /* uart3_rx_m2 */ + <4 RK_PA6 10 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <4 RK_PA5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins =3D + /* uart3_ctsn */ + <1 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins =3D + /* uart3_rtsn */ + <1 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins =3D + /* uart4_rx_m0 */ + <1 RK_PD3 10 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <1 RK_PD2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins =3D + /* uart4_rx_m1 */ + <3 RK_PD0 10 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <3 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins =3D + /* uart4_rx_m2 */ + <1 RK_PB2 10 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PB3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins =3D + /* uart4_ctsn */ + <1 RK_PC7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins =3D + /* uart4_rtsn */ + <1 RK_PC5 10 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins =3D + /* uart5_rx_m0 */ + <4 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <4 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins =3D + /* uart5m0_ctsn */ + <4 RK_PD2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins =3D + /* uart5m0_rtsn */ + <4 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins =3D + /* uart5_rx_m1 */ + <3 RK_PC5 10 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PC4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins =3D + /* uart5m1_ctsn */ + <2 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins =3D + /* uart5m1_rtsn */ + <2 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins =3D + /* uart5_rx_m2 */ + <2 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PD5 10 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins =3D + /* uart6_rx_m1 */ + <1 RK_PA0 10 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <1 RK_PA1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins =3D + /* uart6m1_ctsn */ + <1 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins =3D + /* uart6m1_rtsn */ + <1 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m2_xfer: uart6m2-xfer { + rockchip,pins =3D + /* uart6_rx_m2 */ + <1 RK_PD1 10 &pcfg_pull_up>, + /* uart6_tx_m2 */ + <1 RK_PD0 10 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins =3D + /* uart7_rx_m1 */ + <3 RK_PC1 10 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <3 RK_PC0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins =3D + /* uart7m1_ctsn */ + <3 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins =3D + /* uart7m1_rtsn */ + <3 RK_PC2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins =3D + /* uart7_rx_m2 */ + <1 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m2 */ + <1 RK_PB5 10 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins =3D + /* uart8_rx_m0 */ + <4 RK_PB1 10 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <4 RK_PB0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins =3D + /* uart8m0_ctsn */ + <4 RK_PB3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins =3D + /* uart8m0_rtsn */ + <4 RK_PB2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins =3D + /* uart8_rx_m1 */ + <3 RK_PA3 10 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PA2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins =3D + /* uart8m1_ctsn */ + <3 RK_PA5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins =3D + /* uart8m1_rtsn */ + <3 RK_PA4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8_xfer: uart8-xfer { + rockchip,pins =3D + /* uart8_rx_ */ + <4 RK_PB1 10 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins =3D + /* uart9_rx_m1 */ + <4 RK_PB5 10 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <4 RK_PB4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m1_ctsn: uart9m1-ctsn { + rockchip,pins =3D + /* uart9m1_ctsn */ + <4 RK_PA1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_rtsn: uart9m1-rtsn { + rockchip,pins =3D + /* uart9m1_rtsn */ + <4 RK_PA0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins =3D + /* uart9_rx_m2 */ + <3 RK_PD4 10 &pcfg_pull_up>, + /* uart9_tx_m2 */ + <3 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_ctsn: uart9m2-ctsn { + rockchip,pins =3D + /* uart9m2_ctsn */ + <3 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_rtsn: uart9m2-rtsn { + rockchip,pins =3D + /* uart9m2_rtsn */ + <3 RK_PD2 10 &pcfg_pull_none>; + }; + }; + + vop { + /omit-if-no-ref/ + vop_pins: vop-pins { + rockchip,pins =3D + /* vop_post_empty */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + bt656 { + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins =3D + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpio-func { + /omit-if-no-ref/ + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins =3D + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; --=20 2.38.1 From nobody Sat Jul 27 04:38:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7557DC433FE for ; Thu, 24 Nov 2022 14:49:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229821AbiKXOt4 (ORCPT ); Thu, 24 Nov 2022 09:49:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229612AbiKXOth (ORCPT ); Thu, 24 Nov 2022 09:49:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF35CFF426; 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Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kever Yang , kernel@collabora.com, Yifeng Zhao , Elaine Zhang , Sugar Zhang , Sebastian Reichel Subject: [PATCHv4 3/7] arm64: dts: rockchip: Add base DT for rk3588 SoC Date: Thu, 24 Nov 2022 15:49:24 +0100 Message-Id: <20221124144928.35381-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kever Yang This initial version supports (single core) CPU, dma, interrupts, timers, UART and SDHCI. In short - everything necessary to boot Linux on this system on chip. The DT is split into rk3588 and rk3588s, which is a reduced version (i.e. with less peripherals) of the former. Signed-off-by: Yifeng Zhao Signed-off-by: Elaine Zhang Signed-off-by: Sugar Zhang Signed-off-by: Kever Yang [rebase, squash and reword commit message] Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 58 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1672 +++++++++++++++++++++ 2 files changed, 1730 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi new file mode 100644 index 000000000000..3948597fc8ec --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588s.dtsi" +#include "rk3588-pinctrl.dtsi" + +/ { + gmac0: ethernet@fe1b0000 { + compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg =3D <0x0 0xfe1b0000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_wake_irq"; + clocks =3D <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru CLK_GMAC0_PTP_REF>; + clock-names =3D "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains =3D <&power RK3588_PD_GMAC>; + resets =3D <&cru SRST_A_GMAC0>; + reset-names =3D "stmmaceth"; + rockchip,grf =3D <&sys_grf>; + rockchip,php-grf =3D <&php_grf>; + snps,axi-config =3D <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config =3D <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac0_mtl_tx_setup>; + snps,tso; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,wr_osr_lmt =3D <4>; + snps,rd_osr_lmt =3D <8>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi new file mode 100644 index 000000000000..ecdd2294cd42 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -0,0 +1,1672 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include + +/ { + compatible =3D "rockchip,rk3588"; + + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_l0>; + }; + core1 { + cpu =3D <&cpu_l1>; + }; + core2 { + cpu =3D <&cpu_l2>; + }; + core3 { + cpu =3D <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu =3D <&cpu_b0>; + }; + core1 { + cpu =3D <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu =3D <&cpu_b2>; + }; + core1 { + cpu =3D <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l0>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_l1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l1>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_l2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l2>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_l3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <530>; + clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l3>; + dynamic-power-coefficient =3D <228>; + #cooling-cells =3D <2>; + }; + + cpu_b0: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x400>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b0>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + cpu_b1: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x500>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b1>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + cpu_b2: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x600>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b2>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + cpu_b3: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x700>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache_b3>; + dynamic-power-coefficient =3D <416>; + #cooling-cells =3D <2>; + }; + + idle-states { + entry-method =3D "psci"; + CPU_SLEEP: cpu-sleep { + compatible =3D "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param =3D <0x0010000>; + entry-latency-us =3D <100>; + exit-latency-us =3D <120>; + min-residency-us =3D <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible =3D "cache"; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + next-level-cache =3D <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible =3D "cache"; + cache-size =3D <3145728>; + cache-line-size =3D <64>; + cache-sets =3D <4096>; + }; + }; + + firmware { + optee: optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000010>; + shmem =3D <&scmi_shmem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB01>, + <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates =3D <1200000000>, + <1200000000>; + #clock-cells =3D <1>; + }; + + scmi_reset: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + pmu-a76 { + compatible =3D "arm,cortex-a76-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + spll: clock-0 { + compatible =3D "fixed-clock"; + clock-frequency =3D <702000000>; + clock-output-names =3D "spll"; + #clock-cells =3D <0>; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + xin24m: clock-1 { + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "xin24m"; + #clock-cells =3D <0>; + }; + + xin32k: clock-2 { + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "xin32k"; + #clock-cells =3D <0>; + }; + + pmu_sram: sram@10f000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x0010f000 0x0 0x100>; + ranges =3D <0 0x0 0x0010f000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + scmi_shmem: sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + }; + + sys_grf: syscon@fd58c000 { + compatible =3D "rockchip,rk3588-sys-grf", "syscon"; + reg =3D <0x0 0xfd58c000 0x0 0x1000>; + }; + + php_grf: syscon@fd5b0000 { + compatible =3D "rockchip,rk3588-php-grf", "syscon"; + reg =3D <0x0 0xfd5b0000 0x0 0x1000>; + }; + + ioc: syscon@fd5f0000 { + compatible =3D "rockchip,rk3588-ioc", "syscon"; + reg =3D <0x0 0xfd5f0000 0x0 0x10000>; + }; + + system_sram1: sram@fd600000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xfd600000 0x0 0x100000>; + ranges =3D <0x0 0x0 0xfd600000 0x100000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + cru: clock-controller@fd7c0000 { + compatible =3D "rockchip,rk3588-cru"; + reg =3D <0x0 0xfd7c0000 0x0 0x5c000>; + assigned-clocks =3D + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>; + assigned-clock-rates =3D + <100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <800000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, <500000000>, + <375000000>, <150000000>, + <200000000>; + rockchip,grf =3D <&php_grf>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + i2c0: i2c@fd880000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfd880000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names =3D "i2c", "pclk"; + pinctrl-0 =3D <&i2c0m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@fd890000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfd890000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 6>, <&dmac0 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart0m1_xfer>; + pinctrl-names =3D "default"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0000 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm0m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0010 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm1m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0020 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm2m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfd8b0030 0x0 0x10>; + clocks =3D <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm3m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible =3D "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg =3D <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible =3D "rockchip,rk3588-power-controller"; + #address-cells =3D <1>; + #power-domain-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_NPUTOP { + reg =3D ; + clocks =3D <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>, + <&cru HCLK_NPU_CM0_ROOT>; + pm_qos =3D <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_NPU1 { + reg =3D ; + clocks =3D <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos =3D <&qos_npu1>; + }; + power-domain@RK3588_PD_NPU2 { + reg =3D ; + clocks =3D <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos =3D <&qos_npu2>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg =3D ; + clocks =3D <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + pm_qos =3D <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>, + <&cru ACLK_RKVDEC_CCU>; + pm_qos =3D <&qos_rkvdec0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC1>; + pm_qos =3D <&qos_rkvdec1>; + }; + power-domain@RK3588_PD_VENC0 { + reg =3D ; + clocks =3D <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>; + pm_qos =3D <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_VENC1 { + reg =3D ; + clocks =3D <&cru HCLK_RKVENC1>, + <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>, + <&cru ACLK_RKVENC1>; + pm_qos =3D <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg =3D ; + clocks =3D <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_LOW_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_JPEG_DECODER_ROOT>, + <&cru ACLK_IEP2P0>, + <&cru HCLK_IEP2P0>, + <&cru ACLK_JPEG_ENCODER0>, + <&cru HCLK_JPEG_ENCODER0>, + <&cru ACLK_JPEG_ENCODER1>, + <&cru HCLK_JPEG_ENCODER1>, + <&cru ACLK_JPEG_ENCODER2>, + <&cru HCLK_JPEG_ENCODER2>, + <&cru ACLK_JPEG_ENCODER3>, + <&cru HCLK_JPEG_ENCODER3>, + <&cru ACLK_JPEG_DECODER>, + <&cru HCLK_JPEG_DECODER>, + <&cru ACLK_RGA2>, + <&cru HCLK_RGA2>; + pm_qos =3D <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + + power-domain@RK3588_PD_AV1 { + reg =3D ; + clocks =3D <&cru PCLK_AV1>, + <&cru ACLK_AV1>, + <&cru HCLK_VDPU_ROOT>; + pm_qos =3D <&qos_av1>; + }; + power-domain@RK3588_PD_RKVDEC0 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>; + pm_qos =3D <&qos_rkvdec0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg =3D ; + clocks =3D <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>; + pm_qos =3D <&qos_rkvdec1>; + }; + power-domain@RK3588_PD_RGA30 { + reg =3D ; + clocks =3D <&cru ACLK_RGA3_0>, + <&cru HCLK_RGA3_0>; + pm_qos =3D <&qos_rga3_0>; + }; + }; + power-domain@RK3588_PD_VOP { + reg =3D ; + clocks =3D <&cru PCLK_VOP_ROOT>, + <&cru HCLK_VOP_ROOT>, + <&cru ACLK_VOP>; + pm_qos =3D <&qos_vop_m0>, + <&qos_vop_m1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_VO0 { + reg =3D ; + clocks =3D <&cru PCLK_VO0_ROOT>, + <&cru PCLK_VO0_S_ROOT>, + <&cru HCLK_VO0_S_ROOT>, + <&cru ACLK_VO0_ROOT>, + <&cru HCLK_HDCP0>, + <&cru ACLK_HDCP0>, + <&cru HCLK_VOP_ROOT>; + pm_qos =3D <&qos_hdcp0>; + }; + }; + power-domain@RK3588_PD_VO1 { + reg =3D ; + clocks =3D <&cru PCLK_VO1_ROOT>, + <&cru PCLK_VO1_S_ROOT>, + <&cru HCLK_VO1_S_ROOT>, + <&cru HCLK_HDCP1>, + <&cru ACLK_HDCP1>, + <&cru ACLK_HDMIRX_ROOT>, + <&cru HCLK_VO1USB_TOP_ROOT>; + pm_qos =3D <&qos_hdcp1>, + <&qos_hdmirx>; + }; + power-domain@RK3588_PD_VI { + reg =3D ; + clocks =3D <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>, + <&cru HCLK_ISP0>, + <&cru ACLK_ISP0>, + <&cru HCLK_VICAP>, + <&cru ACLK_VICAP>; + pm_qos =3D <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@RK3588_PD_ISP1 { + reg =3D ; + clocks =3D <&cru HCLK_ISP1>, + <&cru ACLK_ISP1>, + <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>; + pm_qos =3D <&qos_isp1_mwo>, + <&qos_isp1_mro>; + }; + power-domain@RK3588_PD_FEC { + reg =3D ; + clocks =3D <&cru HCLK_FISHEYE0>, + <&cru ACLK_FISHEYE0>, + <&cru HCLK_FISHEYE1>, + <&cru ACLK_FISHEYE1>, + <&cru PCLK_VI_ROOT>; + pm_qos =3D <&qos_fisheye0>, + <&qos_fisheye1>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg =3D ; + clocks =3D <&cru HCLK_RGA3_1>, + <&cru ACLK_RGA3_1>; + pm_qos =3D <&qos_rga3_1>; + }; + power-domain@RK3588_PD_USB { + reg =3D ; + clocks =3D <&cru PCLK_PHP_ROOT>, + <&cru ACLK_USB_ROOT>, + <&cru HCLK_USB_ROOT>, + <&cru HCLK_HOST0>, + <&cru HCLK_HOST_ARB0>, + <&cru HCLK_HOST1>, + <&cru HCLK_HOST_ARB1>; + pm_qos =3D <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + }; + power-domain@RK3588_PD_GMAC { + reg =3D ; + clocks =3D <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + }; + power-domain@RK3588_PD_PCIE { + reg =3D ; + clocks =3D <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + }; + power-domain@RK3588_PD_SDIO { + reg =3D ; + clocks =3D <&cru HCLK_SDIO>, + <&cru HCLK_NVM_ROOT>; + pm_qos =3D <&qos_sdio>; + }; + power-domain@RK3588_PD_AUDIO { + reg =3D ; + clocks =3D <&cru HCLK_AUDIO_ROOT>, + <&cru PCLK_AUDIO_ROOT>; + }; + power-domain@RK3588_PD_SDMMC { + reg =3D ; + pm_qos =3D <&qos_sdmmc>; + }; + }; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible =3D "rockchip,rk3588-qos", "syscon"; + reg =3D <0x0 0xfdf82200 0x0 0x20>; + }; + + gmac1: ethernet@fe1c0000 { + compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg =3D <0x0 0xfe1c0000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_wake_irq"; + clocks =3D <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru CLK_GMAC1_PTP_REF>; + clock-names =3D "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains =3D <&power RK3588_PD_GMAC>; + resets =3D <&cru SRST_A_GMAC1>; + reset-names =3D "stmmaceth"; + rockchip,grf =3D <&sys_grf>; + rockchip,php-grf =3D <&php_grf>; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + snps,tso; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,wr_osr_lmt =3D <4>; + snps,rd_osr_lmt =3D <8>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <2>; + queue0 {}; + queue1 {}; + }; + }; + + sdhci: mmc@fe2e0000 { + compatible =3D "rockchip,rk3588-dwcmshc"; + reg =3D <0x0 0xfe2e0000 0x0 0x10000>; + interrupts =3D ; + assigned-clocks =3D <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC= >; + assigned-clock-rates =3D <200000000>, <24000000>, <200000000>; + clocks =3D <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names =3D "core", "bus", "axi", "block", "timer"; + max-frequency =3D <200000000>; + resets =3D <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names =3D "core", "bus", "axi", "block", "timer"; + status =3D "disabled"; + }; + + gic: interrupt-controller@fe600000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts =3D ; + interrupt-controller; + mbi-alias =3D <0x0 0xfe610000>; + mbi-ranges =3D <424 56>; + msi-controller; + #interrupt-cells =3D <3>; + + ppi-partitions { + interrupt-partition-0 { + affinity =3D < + &cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3 + &cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3 + >; + }; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xfea10000 0x0 0x4000>; + interrupts =3D , + ; + arm,pl330-periph-burst; + clocks =3D <&cru ACLK_DMAC0>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + }; + + dmac1: dma-controller@fea30000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xfea30000 0x0 0x4000>; + interrupts =3D , + ; + arm,pl330-periph-burst; + clocks =3D <&cru ACLK_DMAC1>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + }; + + i2c1: i2c@fea90000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfea90000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c1m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeaa0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c2m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeab0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c3m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeac0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c4m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfead0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c5m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@feb00000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb00000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac0 14>, <&dmac0 15>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@feb10000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb10000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac0 16>, <&dmac0 17>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@feb20000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb20000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac1 15>, <&dmac1 16>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@feb30000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfeb30000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac1 17>, <&dmac1 18>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart1: serial@feb40000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb40000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 8>, <&dmac0 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart1m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart2: serial@feb50000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb50000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 10>, <&dmac0 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart2m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart3: serial@feb60000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb60000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac0 12>, <&dmac0 13>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart3m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart4: serial@feb70000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb70000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac1 9>, <&dmac1 10>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart4m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart5: serial@feb80000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb80000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac1 11>, <&dmac1 12>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart5m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart6: serial@feb90000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeb90000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac1 13>, <&dmac1 14>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart6m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart7: serial@feba0000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfeba0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac2 7>, <&dmac2 8>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart7m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart8: serial@febb0000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfebb0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac2 9>, <&dmac2 10>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart8m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart9: serial@febc0000 { + compatible =3D "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xfebc0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names =3D "baudclk", "apb_pclk"; + dmas =3D <&dmac2 11>, <&dmac2 12>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&uart9m1_xfer>; + pinctrl-names =3D "default"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0000 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm4m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0010 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm5m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0020 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm6m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebd0030 0x0 0x10>; + clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm7m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0000 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm8m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0010 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm9m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0020 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm10m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebe0030 0x0 0x10>; + clocks =3D <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm11m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0000 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm12m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0010 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm13m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0020 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm14m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible =3D "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xfebf0030 0x0 0x10>; + clocks =3D <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names =3D "pwm", "pclk"; + pinctrl-0 =3D <&pwm15m0_pins>; + pinctrl-names =3D "default"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfec80000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c6m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfec90000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c7m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible =3D "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xfeca0000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-0 =3D <&i2c8m0_xfer>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi4: spi@fecb0000 { + compatible =3D "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xfecb0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac2 13>, <&dmac2 14>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-0 =3D <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + dmac2: dma-controller@fed10000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xfed10000 0x0 0x4000>; + interrupts =3D , + ; + arm,pl330-periph-burst; + clocks =3D <&cru ACLK_DMAC2>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + }; + + system_sram2: sram@ff001000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xff001000 0x0 0xef000>; + ranges =3D <0x0 0x0 0xff001000 0xef000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + pinctrl: pinctrl { + compatible =3D "rockchip,rk3588-pinctrl"; + ranges; + rockchip,grf =3D <&ioc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gpio0: gpio@fd8a0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfd8a0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@fec20000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec20000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@fec30000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec30000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@fec40000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec40000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 96 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio4: gpio@fec50000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xfec50000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 128 32>; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + }; +}; + +#include "rk3588s-pinctrl.dtsi" --=20 2.38.1 From nobody Sat Jul 27 04:38:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D46C7C47088 for ; Thu, 24 Nov 2022 14:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229625AbiKXOtm (ORCPT ); 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b=CurWl86nsdpqAjqN2KLzx1vWbtdIxXNFn+sW8lb41EOAZfa9rvJXSH+grjQEy7+Et vXe+95jtFvoUhJbjRjmKNaIQOR8/h5m8byRXVdR1EKo9FUXqKeTS1q8vHdI80CRrlq dLIR1gIZa4KuimjPBr9FkA7YYW4/UqQrF8WVRixB/jBbBUyNSJmaY1Oh1He/Virmsy 3pS231S53sMiGjbOlJ0ANahz0Hbv6fs25HEoGUQ38M+F6l108h3JidrMBnAgHOHrb7 G3qDOqD3yAnQ8e1Lvr3OQXH6/TlO1rgGmfEOunL8NpXXp1zxRVs45iKJaeU97ullpK s8JN4EC0oRnQw== Received: by jupiter.universe (Postfix, from userid 1000) id 62B5648011D; Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, Krzysztof Kozlowski Subject: [PATCHv4 4/7] dt-bindings: arm: rockchip: add initial rk3588 boards Date: Thu, 24 Nov 2022 15:49:25 +0100 Message-Id: <20221124144928.35381-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT binding documentation for the Rockchip RK3588 EVB1, Radxa Rock 5 Model A and B. Co-Developed-by: Christopher Obbard Signed-off-by: Christopher Obbard Acked-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/arm/rockchip.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index c6c69a4e3777..49d442afe67f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -620,6 +620,16 @@ properties: - const: radxa,rock3a - const: rockchip,rk3568 =20 + - description: Radxa Rock 5 Model A + items: + - const: radxa,rock-5a + - const: rockchip,rk3588s + + - description: Radxa Rock 5 Model B + items: + - const: radxa,rock-5b + - const: rockchip,rk3588 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 @@ -704,6 +714,11 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 =20 + - description: Rockchip RK3588 Evaluation board + items: + - const: rockchip,rk3588-evb1-v10 + - const: rockchip,rk3588 + - description: Rockchip RV1108 Evaluation board items: - const: rockchip,rv1108-evb --=20 2.38.1 From nobody Sat Jul 27 04:38:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45E87C4321E for ; Thu, 24 Nov 2022 14:50:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbiKXOt6 (ORCPT ); Thu, 24 Nov 2022 09:49:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229640AbiKXOth (ORCPT ); Thu, 24 Nov 2022 09:49:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F396ACDFE5; Thu, 24 Nov 2022 06:49:35 -0800 (PST) Received: from jupiter.universe (dyndsl-095-033-156-095.ewe-ip-backbone.de [95.33.156.95]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 717B36602B41; Thu, 24 Nov 2022 14:49:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669301374; bh=FCkIJUNWxHQLswUkVDDafLMD8GnKlXSZHgwiboOknos=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gui/IYN7WmTkCj+oB0aDdcXBEweysx0NNoD48ygF3yFNbEvGGxR6cE9hkjG31VKVt d29P6COEtbPAAFArvqWQwfRqjOhUmc4ZRwBWCV/gSc2L/KS1Us26JiAocvkwnNOzeR LQWymMB2Mz5hSM20UrQuWmDj3oFQJLKVtM0mzXLTXsEyYLXmPXKWq9CJW135fqxNiK 1l9MS3LWCTLOgyIDj3GLz0fhF+dLLKlpeDR03YDOw/rVBCHjOKT5bPE7V1ujEPf6Fq QJDelr1gzA+TuImkDmKhEbJTG8Qs1gcvm5eYdwbV2yfz/LvAEaHWiTZf6VjYPi0ylH qN3wriX7U0vzA== Received: by jupiter.universe (Postfix, from userid 1000) id 64C4448011E; Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kever Yang , kernel@collabora.com, Sebastian Reichel Subject: [PATCHv4 5/7] arm64: dts: rockchip: Add rk3588-evb1 board Date: Thu, 24 Nov 2022 15:49:26 +0100 Message-Id: <20221124144928.35381-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kever Yang Add board file for the RK3588 evaluation board. While the hardware offers plenty of peripherals and connectivity this basic implementation just handles things required to successfully boot Linux from eMMC, connect via UART or Ethernet. Signed-off-by: Kever Yang [rebase, update commit message, use EVB1 for SoC bringup] Signed-off-by: Sebastian Reichel Reviewed-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 156 ++++++++++++++++++ 2 files changed, 157 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 8c15593c0ca4..12ed53de11eb 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -72,3 +72,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb1-v10.dts new file mode 100644 index 000000000000..d43d70228d3b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Rockchip RK3588 EVB1 V10 Board"; + compatible =3D "rockchip,rk3588-evb1-v10", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level =3D <200>; + + pwms =3D <&pwm2 0 25000 0>; + power-supply =3D <&vcc12v_dcin>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-rxid"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names =3D "default"; + rx_delay =3D <0x00>; + tx_delay =3D <0x43>; + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; --=20 2.38.1 From nobody Sat Jul 27 04:38:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D56C352A1 for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1669301374; bh=zpRZq7D9RSBYQ50XU0gvhVUUeLk1MXt+/JxhO/9zIbE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WzFd7Ydjjw65O016HcmO7p2qbhVMoxcRXsISb5cVrPRcCnQ+Gw2W84X4kphQTrbUJ q3sAiMDE+GgV2b0RLjquwjB3lNlmielUOblC1+WzRGvq8Q3VZ4XIHrAaG3IIV6K1NK VkCFtr6KFAQ8++08KlVQdARXs/ZLlEHfRdwJzyU0/GXWk/z10nk1/AE5CFaWwMF0SS FiaKxL9M5p9nrjLc1JRvZwp+xAeVp5FFAEpt2/4nv4OVN1d7Y2i+vQJ27noQFi0lGw eYWc48ZhQ3YiyzVEcc+qw6EOeGqCv5KqABZPHR0RDyqQexIzQZb/vzXLN84owSk/mQ wd1W9weoO4Smw== Received: by jupiter.universe (Postfix, from userid 1000) id 66A65480121; Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCHv4 6/7] arm64: dts: rockchip: Add rock-5a board Date: Thu, 24 Nov 2022 15:49:27 +0100 Message-Id: <20221124144928.35381-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add board file for the RK3588s Rock 5A board. While the hardware offers plenty of peripherals and connectivity this basic implementation just handles things required to access eMMC, UART and Ethernet (i.e. enough to successfully boot Linux). Tested-by: Benjamin Gaignard Signed-off-by: Sebastian Reichel Reviewed-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-rock-5a.dts | 63 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 12ed53de11eb..31fa55750a0f 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -73,3 +73,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/= boot/dts/rockchip/rk3588s-rock-5a.dts new file mode 100644 index 000000000000..b9d1ade62b4c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3588s.dtsi" + +/ { + model =3D "Radxa Rock 5A Board"; + compatible =3D "radxa,rock-5a", "rockchip,rk3588s"; + + aliases { + mmc1 =3D &sdhci; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy1>; + phy-mode =3D "rgmii-rxid"; + pinctrl-0 =3D <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names =3D "default"; + rx_delay =3D <0x3e>; + tx_delay =3D <0x3a>; + status =3D "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + /* RTL8211F */ + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; --=20 2.38.1 From nobody Sat Jul 27 04:38:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E86C433FE for ; Thu, 24 Nov 2022 14:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229807AbiKXOtu (ORCPT ); Thu, 24 Nov 2022 09:49:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229581AbiKXOtg (ORCPT ); Thu, 24 Nov 2022 09:49:36 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00D52FAEB2; Thu, 24 Nov 2022 06:49:35 -0800 (PST) Received: from jupiter.universe (dyndsl-095-033-156-095.ewe-ip-backbone.de [95.33.156.95]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 83B156602B43; Thu, 24 Nov 2022 14:49:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669301374; bh=+xOzzxjBpMgXK81/R3EEoYOvapr5v3i2wAM7sTSsSkA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PFtCXiWb8Luo29ODJbiGAXbaKkXa2CMCrz8OBtjU57l+tmQ9US9LSUCvAnleIBQkD vTeW88azVx1gIREiEFwSnmeDLkpLsIoUYvHZ8+HRfskv3hIqSkRK//ogRND5gcx4Wd AvjW9lv0nrcCIAEiIzgqeelTGUhoB8GhOEh8MOhyIv0XnWBmK3FEZ6tDUxuRBCsaCO 6pUqKuI0q9mOj61UB5lRqalZU4TaPqrxkLjkEoP+RnJyZVN+T4FTAJ2NkdGFxuq25X AqnzvoQO+74bcfyQsFlHLB3k1AnBYWsTRPenbIEMiCfBjgjEiLZXT3WdZhd6/sgCDh Tv+JQnhnYbvGQ== Received: by jupiter.universe (Postfix, from userid 1000) id 68900480122; Thu, 24 Nov 2022 15:49:29 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel Subject: [PATCHv4 7/7] arm64: dts: rockchip: Add rock-5b board Date: Thu, 24 Nov 2022 15:49:28 +0100 Message-Id: <20221124144928.35381-8-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124144928.35381-1-sebastian.reichel@collabora.com> References: <20221124144928.35381-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Christopher Obbard Add board file for the RK3588 Rock 5B board. This is a basic implementation which just brings up the eMMC and UART which is enough to successfully boot Linux. The ethernet controller is connected via PCIe so support will come in a follow-up patch. Signed-off-by: Christopher Obbard Signed-off-by: Sebastian Reichel Reviewed-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-rock-5b.dts | 44 +++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 31fa55750a0f..b31aa1b0e9e3 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -73,4 +73,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts new file mode 100644 index 000000000000..baf46bd30b38 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588.dtsi" + +/ { + model =3D "Radxa Rock 5B Board"; + compatible =3D "radxa,rock-5b", "rockchip,rk3588"; + + aliases { + mmc1 =3D &sdhci; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; --=20 2.38.1